WM8955BL Wolfson Microelectronics, WM8955BL Datasheet - Page 36

• Manufacturer Part Number: WM8955BL
• Description: Stereo DAC
• Manufacturer: Wolfson Microelectronics

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WM8955BL
STOPPING THE MASTER CLOCK
In order to minimise power consumed in the digital core of the WM8955BL, the master clock should
be stopped in Standby and OFF modes. If this is cannot be done externally at the clock source, the
DIGENB bit (R25, bit 0) can be set to stop the MCLK signal from propagating into the device core.
However, since setting DIGENB has no effect on the power consumption of other system components
external to the WM8955BL, it is preferable to disable the master clock at its source wherever
possible.
Table 27 ADC and DAC Oversampling Rate Selection
NOTE: Before DIGENB can be set, the control bits DACL and DACR must be set to zero and a
waiting time of 1ms must be observed. Any failure to follow this procedure may prevent DACs and
ADCs from re-starting correctly.
OVERSAMPLING RATE
By default, the oversampling rate of the DAC digital filters is 128x. However, this can be changed to
64x by writing to the DACOSR bit. In the 64x oversampling mode, the digital filters consume less
power. However, the signal-to-noise ratio is slightly reduced.
Table 28 Oversampling Rate Selection
SAVING POWER AT LOW SUPPLY VOLTAGES
The analogue supplies to the WM8955BL can run from 1.8V to 3.6V. By default, all analogue circuitry
on the device is optimized to run at 3.3V. This set-up is also good for all other supply voltages down
to 1.8V. However, at lower voltages, it is possible to save power by reducing the internal bias currents
used in the analogue circuitry. This is controlled as shown below.
Table 29 Analogue Bias Selection
R25 (19h)
Power
Management (1)
R24 (18h)
Additional Control
(2)
R23 (17h)
Additional
Control(1)
REGISTER
ADDRESS
REGISTER
ADDRESS
REGISTER
ADDRESS
7:6
BIT
0
0
VSEL[1:0]
BIT
BIT
LABEL
DIGENB
DACOSR
LABEL
LABEL
DEFAULT
11
0
0
DEFAULT
DEFAULT
Analogue Bias optimization
00 : Lowest bias current, optimized for 1.8V
01 : Low bias current, optimized for 2.5V
10, 11 : Default bias current, optimized for
3.3V
Master clock disable
0: master clock enabled
1: master clock disabled
DAC oversample rate select
1 = 64x (lowest power)
0 = 128x (best SNR)
DESCRIPTION
PD Rev 4.1 February 2007
DESCRIPTION
DESCRIPTION
Production Data
36