AD8304 Analog Devices, AD8304 Datasheet - Page 10

• Manufacturer Part Number: AD8304
• Description: 160 DB Logarithmic Amplifier With Photo-diode Interface
• Manufacturer: Analog Devices

AD8304
Using a value of 0.3 pF for C
fore, the minimum bandwidth at I
While this simple model is useful in making a point, it excludes
other effects that limit its usefulness. For example, the network
R1, C1 in Figure 1, which is necessary to stabilize the system over
the full range of currents, affects bandwidth at all values of I
Later signal processing blocks also limit the maximum value.
TPC 7 shows ac response curves for the AD8304 at eight repre-
sentative currents of 100 pA to 10 mA, using R
C
the full 160 dB dynamic range. More optimal values may be
used for smaller subranges. A certain amount of experimental
trial and error may be necessary to select the optimum input
network component values for a given application.
Turning now to the noise performance of a translinear log amp, the
relationship between I
S
where S
25°C. For an input of 1 nA, S
assuming a 20 kHz bandwidth at this current, the integrated
noise voltage is 70 µVrms. However, the calculation is not com-
plete. The basic scaling of the V
translated to 10 mV/dB, the noise predicted by Equation 14 must
be multiplied by approximately 3.33. The additive noise effects
associated with the reference transistor, Q2, and the temperature
compensation circuitry must also be included. The final voltage
noise spectral density presented at the VLOG pin varies inversely
with I
the measured noise spectral density versus frequency at the
VLOG output, for the same nine decade spaced values of I
Chip Enable
The AD8304 may be powered down by taking the PWDN pin
to a high logic level. The residual supply current in the disabled
mode is typically 60 µA.
USING THE AD8304
The basic connections (Figure 3) include a 2.5:1 attenuator in
the feedback path around the buffer. This increases the basic
slope of 10 mV/dB at the VLOG pin to 25 mV/dB at VLOG.
For the full dynamic range of 160 dB (80 dB optical), the
NSD
1
= 1000 pF. The values for R1 and C1 ensure stability over
, associated with the V
S
PD
NSD
NSD
, but not as simple as square root. TPC
1.6
1.2
0.8
0.4
100p
0
=
is nV/Hz, I
14 7 .
I
PD
1n
PD
10n
PD
and the voltage noise spectral density,
is expressed in microamps and T
BE
100n
J
of Q1, evaluates to the following:
NSD
evaluates to 20 MHz/mA. There-
INPUT – A
BE
1
evaluates to almost 0.5 µV/√Hz;
PD
is approximately 3 mV/dB;
= 100 pA would be 2 kHz.
10
100
1
S
= 750 Ω and
8 and 9 show
1m
10m
A
PD
PD
=
(14)
.
.
output swing is thus 4.0 V, which can be accommodated by the
rail-to-rail output stage when using the recommended 5 V supply.
The capacitor from VLOG to ground forms an optional single-
pole low-pass filter. Since the resistance at this pin is trimmed to
5 kΩ, an accurate time constant can be realized. For example,
with C
filtering is useful in minimizing the output noise, particularly
when I
noise, and are discussed below. A capacitor between VSUM and
ground is essential for minimizing the noise on this node. When
the bias voltage at either VPDB or VREF is not needed these pins
should be left unconnected.
Slope and Intercept Adjustments
The choice of slope and intercept depends on the application.
The versatility of the AD8304 permits optimal choices to be
made in two common situations. First, it allows an input current
range of less than the full 160 dB to use the available voltage span
at the output. Second, it allows this output voltage range to be
optimally positioned to fit the input capacity of a subsequent
ADC. In special applications, very high slopes, such as 1 V/dec,
allow small subranges of I
The slope can be lowered without limit by the addition of a
shunt resistor R
this pin is trimmed to 5 kΩ, the accuracy of the modified slope
will depend on the external resistor. It is calculated using:
For example, using R
per decade or 3.75 mV/dB. Table I provides a selection of suit-
able values for R
NC = NO CONNECT
R1
750
C1
1nF
10nF
I
PD
V
NC
Y
PD
FLT
=
4
3
5
is small. Multipole filters are more effective in reducing
= 10 nF, the –3 dB corner frequency is 3.2 kHz. Such
R
VPDB
VSUM
VSUM
INPT
R
3
5
15
Table I. Examples of Lowering the Slope
VNEG
'
V R
S
S
Y
+
VPS2
(kV)
S
5 Ω
S
from VLOG to ground. Since the resistance at
S
1
k
and the resulting slopes.
PDB
10
S
= 3 kΩ, the slope is lowered to 75 mV
~10k
PWDN
PD
COMPENSATION
ACOM
to be covered at high sensitivity.
TEMPERATURE
BIAS
2
14
V
75
100
150
Y
VPS1
0.5V
(mV/dec)
VREF
VOUT
12
5k
11
VLOG
BFNG
BFIN
13
7
8
9
V
P
VREF
200mV/DEC
RA
15k
10k
CFILT
RB
500mV/DEC
V
OUT
(15)