AD8310 Analog Devices, AD8310 Datasheet - Page 8

• Manufacturer Part Number: AD8310
• Description: Fast Response, DC - 440 Mhz, Voltage Out, 90 DB Logarithmic Amplifier
• Manufacturer: Analog Devices

AD8310
thus alters the intercept. For a 50
gain is about 4.8 and the whole dynamic range moves down
by 13.6 dB. Finally, note that the effective intercept is function of
waveform. For example, a square-wave input will read 6 dB
higher than a sine wave of the same amplitude, and a Gaussian
noise input 0.5 dB higher than a sine wave of the same rms value.
Offset Control
In a monolithic log amp, direct-coupling is used between the
stages for several reasons. First, it avoids the need for coupling
capacitors, which may typically have a chip area at least as large
of that of a basic gain cell, thus considerably increasing die size.
Second, the capacitor values predetermine the lowest frequency
at which the log amp can operate; for moderate values, this may
be as high as 30 MHz, limiting the application range. Third, the
parasitic “back-plate” capacitance lowers the bandwidth of the
cell, further limiting the scope of applications.
However, the very high dc gain of a direct-coupled amplifier
raises a practical issue. An offset voltage in the early stages of
the chain is indistinguishable from a “real” signal. If it were as
high as, say, 400 V, it would be 18 dB larger than the smallest
ac signal (50 V), potentially reducing the dynamic range by this
amount. This problem is averted by using a global feedback path
from the last stage to the first, which corrects this offset in a
similar fashion to the dc negative feedback applied around an
op-amp. The high-frequency components of the feedback signal
must, of course, be removed, to prevent a reduction of the HF
gain in the forward path.
An on-chip filter capacitor of 33 pF provides sufficient suppression
of HF feedback to allow operation above 1 MHz. (The –3 dB
point in the high-pass response is at 2 MHz, but the usable range
extends well below this frequency). To further lower the frequency
range, an external capacitor may be added at Pin OFLT. For
example, 300 pF lowers it by a factor of ten; operation at low
audio frequencies requires a capacitor of about 1 F. Note that
this filter has no effect for input levels well above the offset volt-
age, where the frequency range would extend down to dc (for
a signal applied directly to the input pins). The dc offset can
optionally be nulled by adjusting the voltage on the OFLT pin
(see Applications).
PRODUCT OVERVIEW
The AD8310 comprises six main amplifier/limiter stages. These
six cells, and their and associated g
handle the lower two-thirds of the dynamic range. Three “top-end”
detectors, placed at 14.3 dB taps on a passive attenuator, handle
the upper third of the 95 dB range. The first amplifier stage
provides a low-noise spectral-density (1.28 nV/ Hz). Biasing for
these cells is provided by two references: one determines their gain;
the other is a bandgap circuit that determines the logarithmic
slope, and stabilizes it against supply and temperature variations.
The AD8310 may be enabled/disabled by a CMOS-compatible
level at ENBL (Pin 7).
The differential current-mode outputs of the nine detectors are
summed and then converted to single-sided form, nominally scaled
2 A/dB. The output voltage is developed by applying this current
to 3 k load resistor, followed by a high-speed gain-of-four
buffer amplifier, resulting in a logarithmic slope of 24 mV/dB
(i.e., 480 mV/decade) at VOUT (Pin 4). The unbuffered voltage
m
-styled full-wave detectors,
reactive match, the voltage
–8–
can be accessed at BFIN (Pin 6), allowing certain functional
modifications, including the addition of an external post-
demodulation filter capacitor, and the alteration or adjustment
of slope and intercept.
The last gain stage also includes an offset-sensing cell. This
generates a bipolarity output current should the main signal
path exhibit an imbalance due to accumulated dc offsets. This
current is integrated by an on-chip capacitor, which may be
increased in value by an off-chip component, at OFLT (Pin
3). The resulting voltage is used to null the offset at the output
of the first stage. Since it does not involve the signal input con-
nections, whose ac coupling capacitors otherwise introduce a
second pole in the feedback path, the stability of the offset
correction loop is assured.
The AD8310 is built on an advanced dielectrically-isolated
complementary bipolar process. In the following interface
diagrams, resistors denoted with an uppercase “R” are thin-film
resistors having a low temperature-coefficient of resistance
(TCR) and high linearity under large-signal conditions. Their
absolute tolerance will typically be within 20%. Similarly,
capacitors denoted using an uppercase “C,” have a typical
tolerance of 15% and essentially zero temperature or voltage
sensitivity. Most interfaces have additional small junction
capacitances associated with them, due to active devices or ESD
protection; these may be neither accurate nor stable. Component
numbering in each of these interface diagrams is local.
Enable Interface
The chip-enable interface is shown in Figure 21. The currents
in the diode-connected transistors control the turn-on and turn-
off states of the band-gap reference and the bias generator, and
are a maximum of 100 A when ENBL is taken to 5 V, under
worst-case conditions. For voltages below 1 V, the AD8310 will
be disabled, and consume a sleep current of under 1 A; tied to
the supply, or a voltage above 2 V, it will be fully enabled. The
internal bias circuitry is very fast (typically <100 ns for either
OFF or ON). In practice, however, the latency period before the
log amp exhibits its full dynamic range is more likely to be lim-
ited by factors relating to the use of ac-coupling at the input or
the settling of the offset-control loop (see following sections).
COMMON
SUPPLY
+INPUT
–INPUT
VPOS
INLO
INHI
1.0k
COMM
Figure 20. Main Features of AD8310
8mA
3
NINE DETECTOR CELLS
COMPENSATION LOOP
AMPLIFIER STAGES
SIX 14.3dB 900MHz
SPACED 14.3dB
INPUT-OFFSET
BANDGAP REFERENCE
AND BIASING
2
MIRROR
2 A
/dB
COMM
AD8310
3k
COMM
1k
+
–
COMM
3k
33pF
ENBL
OFLT
VOUT
BFIN
REV. A
ENABLE
BUFFER
INPUT
OUTPUT
OFFSET
FILTER