AT91FR40162S ATMEL Corporation, AT91FR40162S Datasheet - Page 10

• Manufacturer Part Number: AT91FR40162S
• Description: MicroControllers
• Manufacturer: ATMEL Corporation

www.DataSheet4U.com
DataSheet
6.6.2
6.6.3
6.6.4
6.6.5
10
4
U
.com
AT91FR40162S
Boot Mode Select
Remap Command
Abort Control
External Bus Interface
The ARM reset vector is at address 0x0. After the NRST line is released, the ARM7TDMI exe-
cutes the instruction stored at this address. This means that this address must be mapped in
nonvolatile memory after the reset. The input level on the BMS pin during the last 10 clock
cycles before the rising edge of the NRST selects the type of boot memory (see
page
If the embedded Flash memory is to be used as boot memory, the BMS input must be pulled
down externally and NCS0 must be connected to NCSF externally.
The pin BMS is multiplexed with the I/O line P24 that can be programmed after reset like any
standard PIO line.
Table 6-1.
The ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction, Interrupt,
Fast Interrupt) are mapped from address 0x0 to address 0x20. In order to allow these vectors
to be redefined dynamically by the software, the AT91FR40162S uses a remap command that
enables switching between the boot memory and the internal primary SRAM bank addresses.
The remap command is accessible through the EBI User Interface by writing one in RCB of
EBI_RCR (Remap Control Register). Performing a remap command is mandatory if access to
the other external devices (connected to chip selects 1 to 7) is required. The remap operation
can only be changed back by an internal reset or an NRST assertion.
The abort signal providing a Data Abort or a Prefetch Abort exception to the ARM7TDMI is
asserted when accessing an undefined address in the EBI address space.
No abort is generated when reading the internal memory or by accessing the internal peripher-
als, whether the address is defined or not.
The External Bus Interface handles the accesses between addresses 0x0040 0000 and
0xFFC0 0000. It generates the signals that control access to the external devices, and can be
configured from eight 1-Mbyte banks up to four 16-Mbyte banks. It supports byte, half-word
and word aligned accesses.
For each of these banks, the user can program:
• Number of wait states
• Number of data float times (wait time after the access is finished to prevent any bus
• Data bus width (8-bit or 16-bit)
• With a 16-bit wide data bus, the user can program the EBI to control one 16-bit device
contention in case the device is too long in releasing the bus)
(Byte Access Select Mode) or two 8-bit devices in parallel that emulate a 16-bit memory
(Byte Write Access Mode).
3).
BMS
1
0
Boot Mode Select
Boot Memory
External 8-bit memory on NCS0
Internal or External 16-bit memory on NCS0
6174AS–ATARM–25-May-05
Table 3-1 on