LPC1751 NXP Semiconductors, LPC1751 Datasheet
LPC1751
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LPC1751 Summary of contents
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LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 MCU 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN Rev. 04 — 26 January 2010 1. General description The LPC1759/58/56/54/52/51 are ARM Cortex-M3 based microcontrollers for embedded applications featuring ...
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... NXP Semiconductors Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC (LPC1758 only), and the USB interface. This interconnect provides communication with no arbitration delays. Split APB bus allows high throughput with few stalls between the CPU and DMA. ...
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... NXP Semiconductors Repetitive Interrupt Timer (RIT) provides programmable and repeating timed interrupts. Each peripheral has its own clock divider for further power savings. Standard JTAG test/debug interface for compatibility with existing tools. Serial Wire Debug and Serial Wire Trace Port options. ...
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... Ordering options Type number Flash SRAM in kB CPU AHB SRAM0 LPC1759FBD80 512 LPC1758FBD80 512 LPC1756FBD80 256 LPC1754FBD80 128 LPC1752FBD80 LPC1751FBD80 LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 Ethernet USB AHB Total SRAM1 Device/Host/OTG yes Device/Host/OTG 2 ...
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... NXP Semiconductors 5. Block diagram debug JTAG port interface TEST/DEBUG INTERFACE ARM CORTEX-M3 I-code D-code bus bus slave P0, P1, HIGH-SPEED P2, P4 GPIO APB slave group 0 SCK1 SSEL1 SSP1 MISO1 MOSI1 RXD0/TXD0 UART0/1 8 × UART1 RD1/2 CAN1/CAN2 TD1/2 SCL1 I2C1 SDA1 SCK/SSEL SPI0 MOSI/MISO 2 × ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. Pin configuration LQFP80 package 6.2 Pin description Table 3. Pin description Symbol Pin Type P0[0] to P0[31] I/O [1] P0[0]/RD1/TXD3/ 37 I/O SDA1 I O I/O [1] P0[1]/TD1/RXD3/ 38 I/O SCL1 O I I/O [2] P0[2]/TXD0/AD0[ [2] P0[3]/RXD0/AD0[ [1] P0[6]/ 64 I/O I2SRX_SDA/ I/O SSEL1/MAT2[0] I/O O LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/ Description Port 0: Port 32-bit I/O port with individual direction controls for each bit. The operation of Port 0 pins depends upon the pin function selected via the pin connect block ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P0[7]/I2STX_CLK/ 63 I/O SCK1/MAT2[1] I/O I/O O [1] P0[8]/I2STX_WS/ 62 I/O MISO1/MAT2[2] I/O I/O O [1] P0[9]/I2STX_SDA/ 61 I/O MOSI1/MAT2[3] I/O I/O O [1] P0[10]/TXD2/ 39 I/O SDA2/MAT3[0] O I/O O [1] P0[11]/RXD2/ 40 I/O SCL2/MAT3[1] I I/O O [1] P0[15]/TXD1/ 47 I/O SCK0/SCK O I/O I/O [1] P0[16]/RXD1/ 48 I/O SSEL0/SSEL I I/O I/O [1] P0[17]/CTS1/ 46 I/O MISO0/MISO I I/O I/O [1] P0[18]/DCD1/ 45 I/O MOSI0/MOSI I I/O I/O LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 Description P0[7] — ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P0[22]/RTS1/TD1 44 I [2] P0[25]/AD0[2]/ 7 I/O I2SRX _SDA/ I TXD3 I/O O [3] P0[26]/AD0[3]/ 6 I/O AOUT/RXD3 [4] P0[29]/USB_D+ 22 I/O I/O [4] P0[30]/USB_D− 23 I/O I/O P1[0] to P1[31] I/O [1] P1[0]/ 76 I/O ENET_TXD0 O [1] P1[1]/ 75 I/O ENET_TXD1 O [1] P1[4]/ 74 I/O ENET_TX_EN O [1] P1[8]/ 73 I/O ENET_CRS I [1] P1[9]/ 72 I/O ENET_RXD0 I [1] P1[10]/ 71 I/O ENET_RXD1 I [1] P1[14]/ 70 I/O ENET_RX_ER I [1] ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P1[19]/MCOA0/ 26 I/O USB_PPWR O CAP1[ [1] P1[20]/MCI0/ 27 I/O PWM1[2]/SCK0 I O I/O [1] P1[22]/MCOB0/ 28 I/O USB_PWRD/ O MAT1[ [1] P1[23]/MCI1/ 29 I/O PWM1[4]/MISO0 I O I/O [1] P1[24]/MCI2/ 30 I/O PWM1[5]/MOSI0 I O I/O [1] P1[25]/MCOA1/ 31 I/O MAT1[ [1] P1[26]/MCOB1/ 32 I/O PWM1[6]/CAP0[ [1] P1[28]/MCOA2/ 35 I/O PCAP1[0]/ O MAT0[ [1] ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [2] P1[30]/ I/O BUS AD0[ [2] P1[31]/SCK1/ 17 I/O AD0[5] I/O I P2[0] to P2[31] I/O [1] P2[0]/PWM1[1]/ 60 I/O TXD1 O O [1] P2[1]/PWM1[2]/ 59 I/O RXD1 O I [1] P2[2]/PWM1[3]/ 58 I/O CTS1/ O TRACEDATA[ [1] P2[3]/PWM1[4]/ 55 I/O DCD1/ O TRACEDATA[ [1] P2[4]/PWM1[5]/ 54 I/O DSR1/ O TRACEDATA[ [1] P2[5]/PWM1[6]/ 53 I/O DTR1/ O TRACEDATA[ [1] P2[6]/PCAP1[0]/ 52 I/O RI1/TRACECLK ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P2[8]/TD2/ 50 I/O TXD2 O O [1] P2[9]/ 49 I/O USB_CONNECT/ O RXD2 I [5] P2[10]/EINT0/NMI 41 I P4[0] to P4[31] I/O [1] P4[28]/RX_MCLK/ 65 I/O MAT2[0]/TXD3 [1] P4[29]/TX_MCLK/ 68 I/O MAT2[1]/RXD3 [1] TDO/SWO [1] TDI 2 I [1] TMS/SWDIO 3 I I/O [1] TRST 4 I [1] TCK/SWDCLK RSTOUT ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type SSA V 21, 42, I DD(3V3 DD(REG)(3V3 DDA VREFP 10 I VREFN 12 I VBAT tolerant pad providing digital I/O functions with TTL levels and hysteresis. [ tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant ...
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... NXP Semiconductors 7. Functional description 7.1 Architectural overview The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and the D-code bus (see system bus and are used similarly to Tightly Coupled Memory (TCM) interfaces: one bus dedicated for instruction fetch (I-code) and one bus for data access (D-code). The use of two core buses allows for simultaneous operations if concurrent operations target different devices ...
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... NXP Semiconductors The MPU allows separating processing tasks by disallowing access to each other's data, disabling access to memory regions, allowing memory regions to be defined as read-only and detecting unexpected memory accesses that could potentially break the system. The MPU separates the memory into distinct regions and implements protection by preventing disallowed accesses ...
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... RAM (LPC1759/8) 0x1000 4000 16 kB local static RAM (LPC1756/4/2) 0x1000 2000 8 kB local static RAM (LPC1751) 0x1000 0000 reserved 0x0008 0000 512 kB on-chip flash (LPC1759/8) 0x0004 0000 256 kB on-chip flash (LPC1756) 0x0002 0000 ...
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... NXP Semiconductors 7.7 Nested Vectored Interrupt Controller (NVIC) The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 7.7.1 Features • Controls system exceptions and peripheral interrupts • In the LPC1759/58/56/54/52/51, the NVIC supports 33 vectored interrupts • ...
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... NXP Semiconductors 7.9.1 Features • Eight DMA channels. Each channel can support an unidirectional transfer. • 16 DMA request lines. • Single DMA and burst DMA request signals. Each peripheral connected to the DMA Controller can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the DMA Controller. • ...
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... NXP Semiconductors Additionally, any pin on Port 0 and Port 2 (total of 42 pins) providing a digital function can be programmed to generate an interrupt on a rising edge, a falling edge, or both. The edge detection is asynchronous may operate when clocks are not present such as during Power-down mode. Each enabled interrupt can be used to wake up the chip from Power-down mode ...
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... NXP Semiconductors – Receive filtering. – Multicast and broadcast frame support for both transmit and receive. – Optional automatic Frame Check Sequence (FCS) insertion with Cyclic Redundancy Check (CRC) for transmit. – Selectable automatic transmit frame padding. – Over-length frame support for both transmit and receive allows any length frames. ...
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... NXP Semiconductors • While USB is in the Suspend mode, the LPC1759/58/56/54/52/51 can enter one of the reduced power modes and wake up on USB activity. • Supports DMA transfers with all on-chip SRAM blocks on all non-control endpoints. • Allows dynamic switching between CPU-controlled slave and DMA modes. ...
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... NXP Semiconductors 7.13.1 Features • One or two CAN controllers and buses. • Data rates to 1 Mbit/s on each bus. • 32-bit register and RAM access. • Compatible with CAN specification 2.0B, ISO 11898-1. • Global Acceptance Filter recognizes standard (11-bit) and extended-frame (29-bit) receive identifiers for all CAN buses. ...
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... NXP Semiconductors 7.16 UARTs The LPC1759/58/56/54/52/51 each contain four UARTs. In addition to standard transmit and receive data lines, UART1 also provides a full modem control handshake interface and support for RS-485/9-bit mode allowing both software address detection and automatic address detection using 9-bit mode. ...
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... NXP Semiconductors bus during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. ...
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... NXP Semiconductors 2 The I S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I master, and one slave. The I channel, each of which can operate as either a master or a slave. 7.20.1 Features • The interface has separate input/output channels each of which can operate in master or slave mode. • ...
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... NXP Semiconductors • two match registers can be used to generate timed DMA requests. 7.22 Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC1759/58/56/54/52/51. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers ...
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... NXP Semiconductors • Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses. • Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. Software must ‘release’ new match values before they can become effective. • ...
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... NXP Semiconductors 7.25 Repetitive Interrupt (RI) timer The repetitive interrupt timer provides a free-running 32-bit counter which is compared to a selectable value, generating an interrupt when a match occurs. Any bits of the timer/compare can be masked such that they do not contribute to the match detection. The repetitive interrupt timer can be used to create an interrupt that repeats at predetermined intervals ...
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... NXP Semiconductors 7.28 RTC and backup registers The RTC is a set of counters for measuring time when system power is on, and optionally when it is off. The RTC on the LPC1759/58/56/54/52/51 is designed to have extremely low power consumption, i.e. less than 1 μA. The RTC will typically run from the main chip power supply, conserving battery power while the rest of the device is powered up ...
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... NXP Semiconductors LPC17xx MAIN OSCILLATOR (CLKSRCSEL) INTERNAL RC OSCILLATOR 32 kHz RTC OSCILLATOR Fig 4. LPC1759/58/56/54/52/51 clocking generation block diagram 7.29.1.1 Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is trimmed accuracy over the entire voltage and temperature range ...
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... NXP Semiconductors 7.29.2 Main PLL (PLL0) The PLL0 accepts an input clock frequency in the range of 32 kHz to 25 MHz. The input frequency is multiplied high frequency, then divided down to provide the actual clock used by the CPU and/or the USB block. The PLL0 input, in the range of 32 kHz to 25 MHz, may initially be divided down by a value ‘ ...
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... NXP Semiconductors electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient conditions. 7.29.5 Power control The LPC1759/58/56/54/52/51 support a variety of power control features. There are four special modes of processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and Deep power-down mode ...
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... NXP Semiconductors On wake-up from Deep-sleep mode, the code execution and peripherals activities will resume after 4 cycles expire if the IRC was used before entering Deep-sleep mode. If the main external oscillator was used, the code execution will resume when 4096 cycles expire. PLL and clock dividers need to be reconfigured accordingly. ...
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... NXP Semiconductors On the LPC1759/58/56/54/52/51, I/O pads are powered by the 3 the V DD(REG)(3V3) the CPU and most of the peripherals. Depending on the LPC1759/58/56/54/52/51 application, a design can use two power options to manage power consumption. The first option assumes that power consumption is not a concern and the design ties the ...
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... NXP Semiconductors Fig 5. Power distribution 7.30 System control 7.30.1 Reset Reset has four sources on the LPC1759/58/56/54/52/51: the RESET pin, the Watchdog reset, Power-On Reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the ...
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... The APB peripherals are split into two separate APB buses in order to distribute the bus bandwidth and thereby reducing stalls caused by contention between the CPU and the GPDMA controller. 1. LPC1751FBD80 with device ID 25001110 does not support CRP feature. LPC1751FBD80 with device ID 25001118 does support CRP. See errata note in ES_LPC1751. LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 pins ...
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... NXP Semiconductors 7.30.5 AHB multilayer matrix The LPC1759/58/56/54/52/51 use an AHB multilayer matrix. This matrix connects the instruction (I-code) and data (D-code) CPU buses of the ARM Cortex-M3 to the flash memory, the main (32 kB) static RAM, and the Boot ROM. The GPDMA can also access all of these memories ...
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... NXP Semiconductors 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (3.3 V) DD(3V3) V regulator supply voltage (3.3 V) DD(REG)(3V3) V analog 3.3 V pad supply voltage DDA V input voltage on pin VBAT i(VBAT) V input voltage on pin VREFP i(VREFP) ...
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... NXP Semiconductors 9. Thermal characteristics 9.1 Thermal characteristics The average chip junction temperature, T equation amb • ambient temperature (°C), amb • R th(j-a) • sum of internal and I/O power dissipation D The internal power dissipation is the product of I the I/O pins is often small and many times can be negligible. However it can be significant in some applications ...
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... NXP Semiconductors 10. Static characteristics Table 6. Static characteristics − ° ° +85 C, unless otherwise specified. amb Symbol Parameter Supply pins V supply voltage (3.3 V) DD(3V3) V regulator supply voltage DD(REG)(3V3) (3 analog 3.3 V pad supply DDA voltage V input voltage on pin i(VBAT) VBAT V input voltage on pin ...
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... NXP Semiconductors Table 6. Static characteristics …continued − ° ° +85 C, unless otherwise specified. amb Symbol Parameter Standard port pins, RESET I LOW-level input current HIGH-level input IH current I OFF-state output OZ current V input voltage I V output voltage O V HIGH-level input IH voltage ...
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... NXP Semiconductors Table 6. Static characteristics …continued − ° ° +85 C, unless otherwise specified. amb Symbol Parameter USB pins I OFF-state output OZ current V bus supply voltage BUS V differential input DI sensitivity voltage V differential common CM mode voltage range V single-ended receiver th(rs)se switching threshold voltage ...
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... NXP Semiconductors 10.1 Electrical pin characteristics 3 (V) 3.2 2.8 2.4 2.0 Conditions: V Fig 6. Typical HIGH-level output voltage (mA) 10 Conditions: V Fig 7. Typical LOW-level output current I LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/ °C 25 °C −40 ° 3.3 V; standard port pins. DD(REG)(3V3) DD(3V3 0 3.3 V ...
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... NXP Semiconductors (μA) −10 −30 −50 −70 Conditions: V Fig 8. Typical pull-up current (μ −10 Conditions: V Fig 9. Typical pull-down current I LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/ °C 25 °C −40 ° 3.3 V; standard port pins. DD(REG)(3V3) ...
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... NXP Semiconductors 11. Dynamic characteristics 11.1 Flash memory Table 7. Flash characteristics − ° ° +85 C, unless otherwise specified. amb Symbol Parameter N endurance endu t retention time ret [1] Number of program/erase cycles. 11.2 External clock Table 8. Dynamic characteristic: external clock − ° ° +85 C ...
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... NXP Semiconductors 11.3 Internal oscillators Table 9. Dynamic characteristic: internal oscillators − ° ° ≤ + amb DD(3V3) Symbol Parameter f internal RC oscillator frequency osc(RC) f RTC input frequency i(RTC) [1] Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages. ...
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... NXP Semiconductors 2 11.5 I C-bus interface Table 11. Dynamic characteristic: I − ° ° + over specified ranges. amb DD(3V3) Symbol Parameter f SCL clock frequency SCL t fall time f t data set-up time SU;DAT [1] Parameters are valid over operating temperature range unless otherwise specified. ...
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... NXP Semiconductors 2 11.6 I S-bus interface (LPC1759/58/56 only) Table 12. Dynamic characteristics: I − ° ° +85 C. amb Symbol Parameter common to input and output t rise time r t fall time f t pulse width HIGH WH t pulse width LOW WL output t data output valid time ...
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... NXP Semiconductors I2SRX_CLK I2SRX_SDA I2SRX_WS Fig 14. I LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 T cy(clk su(D) 2 S-bus timing (input) Rev. 04 — 26 January 2010 www.DataSheet4U.com 32-bit ARM Cortex-M3 microcontroller h( su(D) su(D) © NXP B.V. 2010. All rights reserved 002aae159 ...
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... NXP Semiconductors 11.7 SSP interface Table 13. Dynamic characteristic: SSP interface ° over specified ranges. amb DD(3V3) Symbol Parameter t SPI_MISO set-up time su(SPI_MISO) [1] The peripheral clock for SSP is PCLK = CCLK = 20 MHz. shifting edges SCK MOSI MISO Fig 15. SSP MISO line set-up time in SPI Master mode ...
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... NXP Semiconductors 11.8 USB interface Table 14. Dynamic characteristics: USB pins (full-speed) Ω pF 1 Symbol Parameter t rise time r t fall time f t differential rise and fall time FRFM matching V output signal crossover voltage CRS t source SE0 interval of EOP FEOPT ...
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... NXP Semiconductors 11.9 SPI Table 15. − amb Symbol T cy(PCLK) T SPICYC t SPICLKH t SPICLKL SPI master t SPIDSU t SPIDH t SPIQV t SPIOH SPI slave t SPIDSU t SPIDH t SPIQV t SPIOH [1] T SPICYC processor clock CCLK. [2] Timing parameters are measured with respect to the 50 % edge of the clock PCLK and the 10 % (90 %) edge of the data signal (MOSI or MISO) ...
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... NXP Semiconductors Fig 18. SPI master timing (CPHA = 0) Fig 19. SPI slave timing (CPHA = 1) LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 SCK (CPOL = 0) SCK (CPOL = 1) t SPIQV DATA VALID MOSI DATA VALID MISO T SPICYC SCK (CPOL = 0) SCK (CPOL = 1) MOSI DATA VALID t SPIQV MISO DATA VALID Rev. 04 — ...
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... NXP Semiconductors Fig 20. SPI slave timing (CPHA = 0) 12. ADC electrical characteristics Table 16. ADC characteristics − ° 2 3 +85 DDA amb Symbol Parameter V analog input voltage IA C analog input capacitance ia E differential linearity error D E integral non-linearity L(adj) E offset error ...
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... NXP Semiconductors 4095 4094 4093 4092 4091 4090 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error ( (4) Integral non-linearity (E ). L(adj) (5) Center of a step of the actual transfer curve. ...
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... NXP Semiconductors The values of resistor components R process-dependent. Fig 22. ADC interface to pins AD0[n] 13. DAC electrical characteristics (LPC1759/58/56/54 only) Table 17. DAC electrical characteristics − ° 2 3 +85 DDA amb Symbol Parameter E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error ...
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... NXP Semiconductors 14. Application information 14.1 Suggested USB interface solutions LPC17xx Fig 23. LPC1759/58/56/54/52/51 USB interface on a self-powered device LPC17xx Fig 24. LPC1759/58/56/54/52/51 USB interface on a bus-powered device LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 microcontroller V DD(3V3) USB_UP_LED USB_CONNECT SoftConnect switch R1 1.5 kΩ V BUS Ω ...
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... NXP Semiconductors RSTOUT LPC1759/58/ SCL1/2 56/54 SDA1/2 EINT0 USB_D+ USB_D− USB_UP_LED Fig 25. LPC1759/58/56/54 USB OTG port configuration USB_UP_LED USB_D+ USB_D− LPC1759/58/ 56/54 USB_PWRD USB_PPWR Fig 26. LPC1759/58/56/54 USB host port configuration LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/ RESET_N ADR/PSW OE_N/INT_N V DD SPEED ...
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... NXP Semiconductors USB_UP_LED USB_CONNECT LPC17xx USB_D+ USB_D− V BUS Fig 27. LPC1759/58/56/54/52/51 USB device port configuration 14.2 XTAL1 input The input voltage to the on-chip oscillators is limited to 1 the oscillator is driven by a clock in slave mode recommended that the input be coupled through a capacitor with C = 100 pF ...
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... NXP Semiconductors 15. Package outline LQFP80: plastic low profile quad flat package; 80 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.16 1.5 0.27 1.6 mm 0.25 0.04 1.3 0.13 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 16. Abbreviations Table 18. Acronym ADC AHB AMBA APB BOD CAN DAC DCC DMA DSP EOP ETM GPIO IRC IrDA JTAG MAC MIIM OTG PHY PLL PWM RMII SE0 SPI SSI SSP TTL UART USB LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 Abbreviations ...
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... NXP Semiconductors 17. Revision history Table 19. Revision history Document ID LPC1759_58_56_54_52_51_4 Modifications: LPC1758_56_54_52_51_3 Modifications: LPC1758_56_54_52_51_2 Modifications: LPC1758_56_54_52_51_1 LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 Release date Data sheet status 20100126 Product data sheet • Added parameters t and t (Section r f • ADC static characteristics: Parameter R • ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Functional description . . . . . . . . . . . . . . . . . . 13 7.1 Architectural overview . . . . . . . . . . . . . . . . . . 13 7.2 ARM Cortex-M3 processor . . . . . . . . . . . . . . . 13 7.3 On-chip flash program memory . . . . . . . . . . . 13 7.4 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 13 7.5 Memory Protection Unit (MPU ...
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... NXP Semiconductors 8 Limiting values Thermal characteristics . . . . . . . . . . . . . . . . . 38 9.1 Thermal characteristics Static characteristics 10.1 Electrical pin characteristics . . . . . . . . . . . . . . 42 11 Dynamic characteristics . . . . . . . . . . . . . . . . . 44 11.1 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . 44 11.2 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 44 11.3 Internal oscillators 11.4 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2 11.5 I C-bus interface 11.6 I S-bus interface (LPC1759/58/56 only 11.7 SSP interface . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.8 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.9 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12 ADC electrical characteristics . . . . . . . . . . . . 53 ...