MT9123 Zarlink Semiconductor, MT9123 Datasheet - Page 17

• Manufacturer Part Number: MT9123
• Description: Dual Voice Echo CANceller ( Itu-t G165 Compliant)
• Manufacturer: Zarlink Semiconductor

Data Sheet
Register Summary
MuteR
MuteS
HPFDis
NBDis
NLPDis
Note: Bits marked as “0” are reserved bits and should be written as indicated.
NB
Active
Down
Conv
DTDet
Extended-
Delay
AdaptDis
Bypass
PAD
BBM
INJDis
Reset
Note: Bits marked as “1” or “0” are reserved bits and should be written as indicated.
Echo Canceller A, Status Register
Echo Canceller B, Status Register
SR
Echo Canceller A, Control Register 1
CRA1
Echo Canceller B, Control Register 1
CRB1
Echo Canceller A, Control Register 2
Echo Canceller B, Control Register 2
CR2
When high, data on Rout is muted to quiet code. When low, Rout carries active code.
When high, data on Sout is muted to quiet code. When low, Sout carries active code.
When high, the offset nulling high pass filters are bypassed in the Rin and Sin paths.
When high, the narrow-band detector is disabled. When low, the narrow-band detector is enabled.
When high, the non-linear processor is disabled.
When low, the offset nulling filters are active and will remove DC offsets on PCM input signals.
When low, the non-linear processors function normally. Useful for G.165 conformance testing.
Logic high indicates the presence of a narrow-band signal on Rin.
Logic high indicates that the power level on Rin is above the threshold level (i.e., low power condition).
Decision indicator for the non-linear processor gain adjustment.
Decision indicator for rapid adaptation convergence. Logic high indicates a rapid convergence state.
Logic high indicates the presence of a double-talk condition.
When high, Echo Cancellers A and B are internally cascaded into one 128ms echo canceller.
When high, echo canceller adaptation is disabled.
When high, Sin data is by-passed to Sout and Rin data is by-passed to Rout.
When high, 12dB of attenuation is inserted into the Rin to Rout path.
When high the Back to Back configuration is enabled.
When high, the noise injection process is disabled. When low noise injection is enabled.
When high, the power-up initialization is executed presetting all register bits including this bit.
When low, Echo Cancellers A and B operate independently.
Do not enable both Extended-Delay and BBM configurations at the same time.
When low, the echo canceller dynamically adapts to the echo path characteristics.
When low, output data on both Sout and Rout is a function of the echo canceller algorithm.
When low the Rin to Rout path gain is 0dB.
When low the Normal configuration is enabled. Do not enable Extended-Delay and BBM configurations at the same time.
Always set both BBM bits of the two echo cancellers to the same logic value to avoid conflict.
Reset
Reset
7
7
0
7
7
INJDis
INJDis
6
6
0
6
6
NLPDis
DTDet
BBM
BBM
5
5
5
5
Conv
PAD
PAD
4
4
0
4
4
Bypass
Bypass
NBDis
Down
3
3
3
3
AdaptDis
AdaptDis
HPFDis MuteS
Active
2
2
2
2
1
1
1
1
1
0
Extended
Delay
MuteR
ADDRESS = 00h WRITE/READ VERIFY
ADDRESS = 01h WRITE/READ VERIFY
ADDRESS = 20h WRITE/READ VERIFY
ADDRESS = 21h WRITE/READ VERIFY
NB
0
0
0
0
0
ADDRESS = 02h READ
ADDRESS = 22h READ
Power Reset Value
Power Reset Value
Power Reset Value
Power Reset Value
0000 0000
0000 0010
0000 0000
0000 0000
MT9123
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