MT9123 Zarlink Semiconductor, MT9123 Datasheet - Page 3

• Manufacturer Part Number: MT9123
• Description: Dual Voice Echo CANceller ( Itu-t G165 Compliant)
• Manufacturer: Zarlink Semiconductor

Data Sheet
Pin Description (continued)
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Pin #
10
11
12
13
14
15
16
17
18
4
5
6
7
8
9
FORMAT ITU-T/Sign Mag (Input). An active low selects sign-magnitude PCM code. When high,
PWRDN Power-down (Input). An active low resets the device and puts the MT9123 into a low-power
MCLK
Name
ENB2
S4/S3
SCLK
LAW
VSS
NLP
Rin
Sin
IC1
IC2
IC3
IC4
CS
SSI Enable Strobe / ST-BUS Mode for Sin/Rout (Input). This pin has dual functions
depending on whether SSI or ST-BUS is selected.
For SSI, this is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial
PCM data transfer for Echo Canceller B on Sin/Rout pins. Strobe period is 125 microseconds.
For ST-BUS, this pin, in conjunction with the ENA2 pin, will select the proper ST-BUS mode
for Sin/Rout pins (see ST-BUS Operation description). The selected mode applies to both
Echo Canceller A and B.
Receive PCM Signal Input (Input). 128 kbit/s to 4096 kbit/s serial PCM input stream. Data
may be in either companded or 2’s complement linear format. Two PCM channels are time-
multiplexed on this pin. These are the Receive Input reference channels for Echo Cancellers
A and B. Data bits are clocked in following SSI or ST-BUS timing requirements.
Send PCM Signal Input (Input). 128 kbit/s to 4096 kbit/s serial PCM input stream. Data may
be in either companded or 2’s complement linear format. Two PCM channels are time-
multiplexed on this pin. These are the Send Input channels (after echo path) for Echo
Cancellers A and B. Data bits are clocked in following SSI or ST-BUS timing requirements.
Digital Ground. Nominally 0 volts.
Master Clock (Input). Nominal 20 MHz Master Clock input. May be connected to an
asynchronous (relative to frame signal) clock source.
Internal Connection 1 (Input). Must be tied to Vss.
Non-Linear Processor Control (Input).
Controllerless Mode: An active high enables the Non-Linear Processors in Echo Cancellers A
and B. Both NLP’s are disabled when low. Intended for conformance testing to G.165 and it is
usually tied to Vdd for normal operation.
Controller Mode: This pin is ignored (tie to Vdd or Vss). The non-linear processor operation is
controlled by the NLPDis bit in Control Register 2. Refer to the Register Summary.
Internal Connection 2 (Input). Must be tied to Vss.
A/µ Law Select (Input). An active low selects µ−Law companded PCM. When high, selects
A-Law companded PCM. This control is for both echo cancellers and is valid for both
controller and controllerless modes.
selects ITU-T (G.711) PCM code. This control is for both echo cancellers and is valid for both
controller and controllerless modes.
stand-by mode.
Internal Connection 3 (Output). Must be left unconnected.
Internal Connection 4 (Output). Must be left unconnected.
Selection of Echo Canceller B Functional States (Input).
Controllerless Mode: Selects Echo Canceller B functional states according to Table 2.
Controller Mode: S4 and S3 pins become SCLK and CS pins respectively.
Serial Port Synchronous Clock (Input). Data clock for the serial microport interface.
Chip Select (Input). Enables serial microport interface data transfers. Active low.
Description
MT9123
3