MT9161 Zarlink Semiconductor, MT9161 Datasheet - Page 5

• Manufacturer Part Number: MT9161
• Description: 5 V Multi-featured Phone Codec With Programmable U/a Law Companding
• Manufacturer: Zarlink Semiconductor

Advance Information
(DATA2), a chip select pin (CS) and a synchronous
data clock pin (SCLK). For D-channel contention
control, in ST-BUS mode, this interface provides an
open-drain interrupt output (IRQ).
The microport dynamically senses the state of the
serial clock (SCLK) each time chip select becomes
active. The device then automatically adjusts its
internal timing and pin configuration to conform to
Intel or Motorola/National requirements. If SCLK is
high during chip select activation then Intel mode 0
timing is assumed. The DATA1 pin is defined as a
bi-directional
DATA2 is internally disconnected. If SCLK is low
during chip select activation then Motorola/National
timing is assumed. Motorola processor mode
CPOL=0, CPHA=0 must be used. DATA1 is defined
as the data transmit pin while DATA2 becomes the
data receive pin. Although the dual port Motorola
controller configuration usually supports full-duplex
communication, only half-duplex communication is
possible in the MT9160B/61B. The micro must
discard non-valid data which it clocks in during a
valid write transfer to the MT9160B/61B. During a
valid read transfer from the MT9160B/61B data
simultaneously clocked out by the micro is ignored
by the MT9160B/61B.
Serial Port
PCM
D
PCM
D
in
out
(transmit/receive)
Encoder
-2.05dB
Decoder
2.05dB
Transmit Filter
(1 dB steps)
Transmit Filter
(1 dB steps)
0 to +7 dB
0 to +7 dB
(1 dB steps)
Gain
Filter Gain
0 to -7 dB
Gain
Receive
Filter/Codec and Transducer Interface
serial
INTERNAL TO DEVICE
Figure 3 - Audio Gain Partitioning
port
-0.37 dB or 8.93 dB
Transmit Gain
(3.32 dB steps)
Side-tone
+9. 96 dB
-11 dB
-9.96 to
and
-6 dB
Default Bypass
All data transfers through the microport are two-byte
transfers requiring the transmission of a Command/
Address byte followed by the data byte written or
read from the addressed register. CS must remain
asserted for the duration of this two-byte transfer. As
shown in Figures 5 and 6 the falling edge of CS
indicates to the MT9160B/61B that a microport
transfer is about to begin. The first 8 clock cycles of
SCLK after the falling edge of CS are always used to
receive the Command/Address byte from the
microcontroller.
contains information detailing whether the second
byte transfer will be a read or a write operation and
at what address. The next 8 clock cycles are used to
transfer the data byte between the MT9160B/61B
and the microcontroller. At the end of the two-byte
transfer CS is brought high again to terminate the
session. The rising edge of CS will tri-state the
output driver of DATA1 which will remain tri-stated as
long as CS is high.
Intel processors utilize least significant bit first
transmission while Motorola/National processors
employ most significant bit first transmission. The
MT9160B/61B
accommodates these two schemes for normal data
bytes. However, to ensure decoding of the R/W and
address information, the Command/Address byte is
defined differently for Intel operation than it is for
Transmit
8.42 dB
Gain
-8.05 dB or
Receiver
-2.05 dB
Driver
The
microport
HSPKR +
HSPKR -
Command/Address
EXTERNAL TO DEVICE
M+
MT9160B/61B
M-
75
75
Transmitter
Microphone
automatically
Receiver
Handset
(150 )
byte
83