MT9161 Zarlink Semiconductor, MT9161 Datasheet - Page 9

• Manufacturer Part Number: MT9161
• Description: 5 V Multi-featured Phone Codec With Programmable U/a Law Companding
• Manufacturer: Zarlink Semiconductor

Advance Information
IRQ
FP
DSTo/
DSTi
Di-bit Group
Receive
D-Channel
FP
C4i
C2
IRQ
Di-bit Group
Receive
D-Channel
DSTo/
DSTi
* note that frame n+4 is equivalent to frame n of the next cycle.
IRQ
FP
D0
D0
n-7
I
n-3
I
No preset value
No preset value
8 kb/s operation
D1
D1
n-6
II
D0
D2
D2
III
n-5
II
n-2
D3
IV
n-4
D3
Figure 7c - D-Channel 8 kb/s Operation
Figure 7a - D-Channel 16 kb/s Operation
D4
16 kb/s operation
n-3
V
D4
D1
Figure 7b - IRQ Timing Diagram
III
n-1
D5
VI
n-2
Di-bit Group
D5
D-Channel
D6
VII
Transmit
n-1
D6
Di-bit Group
D-Channel
VIII
D7
Transmit
IV
n
n
t
D0
if
D7
Microport Read/Write Access
n+1
I
=500 nsec max
Power-up reset to 1111 1111
D0
D1
n+2
II
n+1
I
Microport Read/Write Access
D2
III
n+3
D1
Microport Read/Write Access
D3
IV
n+4
D2
Power-up reset to 1111 1111
II
D4
n+2
n+5
V
D3
D5
VI
n+6
D4
MT9160B/61B
D6
VII
or next FP, whichever occurs first
n+7
III
n+3
Read/Write of Address 04 Hex
VIII
D7
n+8
D5
Reset coincident with
t
R
D6
ir
pullup
=500 nsec max
D-Channel
IV
n+4*
= 10 k
D7
87