MT92220 Zarlink Semiconductor, MT92220 Datasheet - Page 141

• Manufacturer Part Number: MT92220
• Description: 1023 Channel Voice Over IP/AAL2 Processor
• Manufacturer: Zarlink Semiconductor

Data Sheet
When an HDLC packet completes, an event must be written to the Assembly Event Queue so the packet makes it
to the network interface. Each HDLC Stream has an entry in the HDLC Stream to HDLC Address LUT Structure,
which gives, for each HDLC Stream, the list of all HDLC addresses and their corresponding TX Connection
Structures. For each Stream, the number of valid addresses is defined (anywhere from 16 to 512 in increments of
16) as well as a pointer to the corresponding HDLC Address LUT.
The format of the HDLC Stream to HDLC Address LUT Structure is the following:
HDLC Address
LUT Base for
HDLC Stream
Add Range
Note
Field
4007FCh
4007FEh
4007FAh
400000h
400002h
400004h
400006h
4007F8h
This field serves to locate in external SSRAM A a look-up table used to associated
HDLC addresses with TX Connection Structures. It points to 64-byte increments.
Defines the size of the HDLC Address LUT Structure. “00000” = address ranges
between 0 and 511; “00001” = address ranges between 0 and 15; “00010” = address
ranges between 0 and 31; “00011” = address ranges between 0 and 47; ... ; ”11111” =
address ranges between 0 and 495.
Indexing in this structure is done implicitly using the HDLC stream number in the TX
TDM Control Memory. This table is consulted every time an HDLC packet reception
completed.
Figure 77 - HDLC Stream to HDLC Address LUT Structure
b 15
b14
HDLC Address LUT Base [20:6] for HDLC Stream 510
HDLC Address LUT Base [20:6] for HDLC Stream 511
Table 58 - Fields and Description
b13
HDLC Address LUT Base [20:6] for HDLC Stream 0
HDLC Address LUT Base [20:6] for HDLC Stream 1
b12
b11
Zarlink Semiconductor Inc.
b10
b9
b8
Description
b7
b6
b5
b4
b3
Add Range
Add Range
Add Range
Add Range
b2
b1
b0
MT92220
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