MT93L16 Mitel Networks Corporation, MT93L16 Datasheet - Page 9

• Manufacturer Part Number: MT93L16
• Description: CMOS Low-voltage Acoustic Echo CANceller
• Manufacturer: Mitel Networks Corporation

Preliminary Information
Linear PCM
The 16-bit 2’s complement PCM linear coding
permits a dynamic range beyond that which is
specified in ITU-T G.711 for companded PCM. The
echo-cancellation algorithm will accept 16 bits 2’s
complement linear code which gives a maximum
signal level of +15dBm0.
Note that the two ports are independent so that, for example, PORT1 can operate with 8-bit enable strobes and PORT2 can operate
with 16-bit enable strobes.
PCM Code
+ Full Scale
- Full Scale
+ Zero
- Zero
PORT2
BCLK
PORT1
ENA1
Rin
Sout
ENA2
Rout
Sin
Table 4 - Companded PCM
Sign-Magnitude
LAW = 0 or 1
FORMAT=0
1111 1111
1000 0000
0000 0000
0111 1111
outputs = High impedance
/A-LAW
inputs = don’t care
1000 0000
1111 1111
0111 1111
0000 0000
LAW = 0
-LAW
ITU-T (G.711)
FORMAT=1
1010 1010
1101 0101
0101 0101
0010 1010
LAW =1
A-LAW
Figure 7 - SSI Operation
8 or 16 bits
8 or 16 bits
8 or 16 bits
8 or 16 bits
start of frame (SSI)
EC
EC
Bit Clock (BCLK/C4i )
The BCLK/C4i pin is used to clock the PCM data for
GCI and ST-BUS (C4i) interfaces, as well as for the
SSI (BCLK) interface.
In SSI operation, the bit rate is determined by the
BCLK frequency. This input must contain either eight
or sixteen clock cycles within the valid enable strobe
window. BCLK may be any rate between 128 KHz to
4.096 MHz and can be discontinuous outside of the
enable strobe windows defined by ENA1, ENA2 pins.
Incoming PCM data (Rin, Sin) are sampled on the
falling edge of BCLK while outgoing PCM data (Sout,
Rout) are clocked out on the rising edge of BCLK.
See Figure 13.
In ST-BUS and GCI operation, connect the system
C4 (4.096MHz) clock to the C4i pin.
Master Clock (MCLK)
A nominal 20MHz, continuously-running master
clock
asynchronous with the 8KHz frame.
(MCLK)
is
required.
MCLK
MT93L16
may
be
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