MT8930C Zarlink Semiconductor, MT8930C Datasheet - Page 18

• Manufacturer Part Number: MT8930C
• Description: 4 Wire Full-duplex 2B+D (192 Kbps) Data Format Isdn S And T Subscriber Network Interface Circuit With Controllerless Mode
• Manufacturer: Zarlink Semiconductor

distinguished by the fact that it has no “Last Byte”
status on any of its bytes.
iv) Idle Channel
While receiving the idle channel, the idle bit in the
HDLC status register remains set.
v) Transparent Data Transfer
By setting the Trans bit in the HDLC Control Register
2 to select the transparent data transfer, the receive
section will disable the protocol functions like Flag/
Abort/Idle detection, zero deletion, CRC calculation
and address comparison. The received data is
shifted in from the active port and written to receive
FIFO in bytewide format.
It should be noted that none of the protocol related
status or interrupt bits are applicable in transparent
data transfer state.
Note 1:
Note 2:
B5-B0
B6-B3
18
BIT
BIT
B7
B6
B7
B2
B1
B0
These bits have no designated memory space and will read as the last values written to the microprocessor port.
The transmission of M=1 is used for a second level of multiframing.
IRQ/NDA
NAME
RxDIS
NAME
M/Sen
NA
P/SC
NA
NA
NA
(1)
Keep at ‘0’ for normal operation.
When set to ‘1’, this bit disables the S-Bus signal receiver. It can be used, for example, to
force INFO4 to INFO2 transition in the NT state machine while receiving INFO3 from the
TE.
Keep at ‘0’ for normal operation.
A ‘1’ will allow access to Control Register 1 and Master Status Register.
A ‘0’ will prevent it.
Keep at ’0’ for normal operation.
The state of this pin will select the mode of the IRQ/NDA pin.
A ’0’ will enable the IRQ pin for HDLC interrupts.
A ’1’ will enable the New Data Available signal which identifies the access time to the
synchronous registers. (If NDA is enabled, the HDLC interrupts are disabled.)
A ’0’ will enable the transmission of the M
Register (refer to Table 13). The selection of M or S is determined by the HALF signal
(refer to functional timing).
A ’1’ will disable this feature forcing the M and S bits to binary zero.
The Parallel/Serial Control bit selects the source of the control channel. If ’0’, then the C-
channel Register is access through the ST-BUS stream. If ’1’, then the C-channel
Register is accessed through the microprocessor port.
Table 3. Master Control Register (Read/Write Add. 00000
However, the FIFO related
Table 4. Control Register 1 (Write Add. 10000
status and interrupt bits are pertinent and carry the
same meaning as they do while performing the
protocol functions.
vi) Receive Overflow
Receive overflow occurs when the receive section
attempts to load a byte to an already full receive
FIFO. All attempts to write to the full FIFO will be
ignored until the receive FIFO is read.
overflow occurs, the rest of the present packet is
ignored as the receiver will be disabled until the
reception of the next opening flag.
DESCRIPTION
DESCRIPTION
(2)
or S bit as selected in the NT Mode C-channel
B
)
B
)
Data Sheet
When