MT8930C Zarlink Semiconductor, MT8930C Datasheet - Page 24

• Manufacturer Part Number: MT8930C
• Description: 4 Wire Full-duplex 2B+D (192 Kbps) Data Format Isdn S And T Subscriber Network Interface Circuit With Controllerless Mode
• Manufacturer: Zarlink Semiconductor

MT8930C
Note 1:
Note 2:
24
B7-B6
B2-B1
BIT
BIT
B7
B6
B5
B4
B3
B2
B1
B0
B5
B4
B3
B0
Allow one ST-BUS frame to input the C-channel and one ST-BUS frame to establish the connection.
The C-channel Control Register is updated once every ST-BUS frame. Therefore, this register should not be written to
more than once per frame, otherwise, the last access will override previous ones.
TxMCH
RegSel
Table 16. TE Mode C-channel Control Register
RegSel
Priority
NAME
NAME
ClrDia
FSync
DReq
DinB
Loop
FLv
Idle
AR
DR
NA
Table 17. TE Mode Diagnostic Register (Write Add. 01000
Setting this bit will initiate the activation of the S-Bus.
If ’0’, the device will remain in the present state.
Setting this bit will initiate the deactivation of the S-Bus.
If ’0’, the device will remain in the present state. This bit has priority over AR.
If ’1’, the D-channel will be placed in the B1 timeslot allocating 64 kbit/s to the
D-channel.
If ’0’, the D-channel will assume its position with a 16 kbit/s bandwidth.
The status of this bit selects the priority class of the terminal equipment. A ’1’ selects the
high priority and a ’0’ selects the low priority.
This bit is used to request or relinquish the D-channel on the S-Bus when the D-channel
source is the ST-BUS. A ’1’ will request the D-channel, a ’0’ will relinquish it.
Keep at ’0’ when the D-channel source is the HDLC transmitter.
The state of this bit will be transmitted in the maintenance channel (Q-channel).
A ’1’ will clear the contents of the Diagnostics Register.
A ’0’ will enable the maintenance functions found in the Diagnostic Register.
This bit should be set to 1 as long as the device is not fully active (IS0, IS1 ≠ 1,1).
If the register select bit is set to ’1’, the control register is redefined as the diagnostic
Register. A ’0’ gives access to the Control Register.
The status of these two bits determine which type of loopback is to be performed:
If ’1’, the device will maintain frame synchronization even after losing the frame sync
sequence (i.e., if the device is transmitting INFO3 and this bit is set, INFO3 will still be
transmitted even if the frame sync sequence in the received signal is lost).
If ’0’, synchronization will be declared when three consecutive framing sequences have
been detected.
If ’1’, the frame sync sequence will violate the normal bipolar encoding rule.
If ’0’, the framing pattern resumes normal operation, i.e., framing bit will be a bipolar
violation.
If ’1’, an all 1s signal is transmitted on the line.
If ’0’, the transmitter will resume normal operation.
Unused.
If the register select bit is set to ’1’, the control register is redefined as the diagnostic
register. A ’0’ gives access to the control register.
(1)
B7 - B6
0 - 0 - no loopback active
0 - 1 - near end loopback LTx to LRx
1 - 0 - digital loopback DSTi to DSTo
1 - 1 - remote loopback LRx to LTx
DESCRIPTION
DESCRIPTION
(2)
(Write Add. 01000
B
and B0 = 1)
B
and B0 = 0)
(1)
Data Sheet