MT8931C Zarlink Semiconductor, MT8931C Datasheet - Page 22

• Manufacturer Part Number: MT8931C
• Description: 4 Wire Full-duplex 2B+D (192 Kbps) Data Format Isdn S And T Subscriber Network Interface Circuit
• Manufacturer: Zarlink Semiconductor

Note 1:
Note 2:
22
B7-B6
B6-B5
B3-B0
BIT
BIT
B5
B4
B3
B2
B1
B0
B7
B4
Bus activity is set when three zeros are received in a time period equivalent to 48 bits or 250
The Status Register is updated internally once every ST-BUS frame. Therefore, more than one read access per frame will
consecutive ones are received.
return the same value.
Table 14. NT Mode C-channel Diagnostic Register (Write Add. 01000
Sync/BA
RxMCH
RegSel
IS0-IS1
NAME
NAME
FSync
Slave
Echo
Loop
FLv
Idle
NA
The status of these two bits determine which type of loopback is to be performed:
If ’1’, the device will maintain frame synchronization even after losing the frame sync
sequence (i.e., if the device is transmitting INFO2 or INFO4 and this bit is set, the same
INFO signal will still be transmitted even if the frame sync sequence in the received signal
is lost).
If ’0’, synchronization will be declared when three consecutive framing sequences have
been detected without error.
If ’1’, the frame sync sequence will violate the bipolar violation encoding rule.
If ’0’, the framing pattern resumes normal operation, i.e., Framing bit is a bipolar violation.
Setting this bit to ’1’ will force an all 1s signal to be transmitted on the line.
Setting this bit to ’1’ will force all D-echo bits (E) to zero.
If ’1’, the device will operate in a NT slave mode. This allows the device to be used at the
terminal equipment end of the line while receiving its clocks from an external source.
If the register select bit is set to ’1’, the control register is redefined as the diagnostic
register. A ’0’ gives access to the control register.
This bit is set when the device has achieved frame synchronization while the activation
request is asserted (DR = 0 and AR = 1). If there is a deactivation request or AR is low
(DR = 1 or AR = 0), this bit indicates the presence of bus activity
identifies the reception of INFO frames (INFO1 or INFO3).
Binary encoded state sequence.
Following a ‘0’ input at the HALF pin or HALF bit in the C-channel Control Register, the
state of this bit reflects the received maintenance Q-channel (received in the Fa bit
position during multiframing).
This bit will always read ‘1’ if multiframing is not used.
These bits will read
Table 15. NT Mode Status Register
B7 - B6
0 - 0
0 - 1
1 - 0
1 - 1
IS0 - IS1
0 -
0 -
1 -
1 -
0
1
0
1
’1’.
- no loopback active
- near end loopback LTx to LRx
- digital loopback DSTi to DSTo
- remote loopback LRx to LTx
- deactivated
- pending deactivation
- pending activation
- activated
DESCRIPTION
DESCRIPTION
(2)
(Read Add. 01001
B
(1)
)
B
µ
and B0 = 1)
. A bus activity
s. It is reset when 128
Data Sheet