MT8931CP Zarlink Semiconductor, MT8931CP Datasheet - Page 11

• Manufacturer Part Number: MT8931CP
• Description: Description = 4 Wire Full-duplex 2B+D (192Kb/s) Data Format Isdn S And T Subscriber Network Interface Circuit ;; Package Type = Pdip ;; No. Of Pins = 28
• Manufacturer: Zarlink Semiconductor

Data Sheet
situation is when the system is trying to synchronize
two nodes of a synchronous network. This allows
multiple TEs to share a common ST-BUS timebase.
The synchronization of the loops is established by
using the clock signals produced by a local TE as an
input timing source to the NT slave.
Adaptive Timing Operation
On power-up or after a reset, the SNIC in NT mode is
set to operate in fixed timing. To switch to adaptive
timing, the user should:
Switching from adaptive timing mode is completed
by resetting the Timing bit.
ST-BUS Clock
ST-BUS Stream
Frame Pulse
Frame Pulse
1) set the DR bit to 1
2) set the Timing bit to 1 in the C-channel
3) wait for 100 ms period
4) proceed in using the AR and DR bits as
ST-BUS
Stream
System
System
Input
Control Register
desired
to TE
to TE
F0b
MT8931C
to TE
NT
F0od
Channel 0 - 3
Active on
Figure 13 - Daisy Chaining the SNIC
MT8931C
MT8931C
Figure 14 - NT in Star Configuration
NT
NT
STAR
STAR
DSTi
DSTi
F0b
F0b
F0b
MT8931C
to TE
V
NT
DD
F0od
Channels 4 - 7
Active on
ST-BUS Interface
The ST-BUS is a synchronous time division
multiplexed serial bussing scheme with data streams
operating at 2048 kbit/s configured as 32, 64 kbit/s
channels (refer to Fig. 11). Synchroni-zation of the
data transfer is provided from a frame pulse which
identifies the frame boundaries and repeats at an 8
kHz rate.
(F0b) defines the ST-BUS frame boundaries. All
data is clocked into the device on the rising edge of
the 4096 kHz clock (C4b) three quarters of the way
into the bit cell, while data is clocked out on the
falling edge of the 4096 kHz clock at the start of the
bit cell.
All timing signals (i.e. F0b & C4b) are identified as
bidirectional (denoted by the terminating b). The
I/O configuration of these pins is controlled by the
mode of operation (NT or TE). In the NT mode, all
synchronized signals are supplied from an external
source and the SNIC uses this timing while
transferring information to and from the S or
ST-BUS.
phase-locked loop extracts timing from the received
data on the S-Bus and
4096 kHz (C4b) and frame pulse (F0b).
analog phase-locked loop also maintains proper
phase relation between the timing signals as well as
STAR
F0b
DSTi
DSTo
STAR
F0b
DSTi
F0b
MT8931C
MT8931C
MT8931C
to TE
NT
NT
NT
F0od
Channels 8 - 11
In the TE mode,
Figure 4 shows how the frame pulse
Active on
to TE
to TE
F0b
MT8931C
to TE
NT
generates
F0od
Channels 12 - 15
an on-board analog
ST-BUS Stream
Active on
Output
the
system
The
11