MT8931CP Zarlink Semiconductor, MT8931CP Datasheet - Page 17

• Manufacturer Part Number: MT8931CP
• Description: Description = 4 Wire Full-duplex 2B+D (192Kb/s) Data Format Isdn S And T Subscriber Network Interface Circuit ;; Package Type = Pdip ;; No. Of Pins = 28
• Manufacturer: Zarlink Semiconductor

Data Sheet
Note 1:
Note 2:
B6-B3
B5-B0
BIT
BIT
B7
B2
B1
B0
B7
B6
These bits have no designated memory space and will read as the last values written to the microprocessor port.
The transmission of M=1 is used for a second level of multiframing.
IRQ/NDA
NAME
M/Sen
NAME
RxDIS
NA
P/SC
NA
NA
NA
(1)
A ‘1’ will allow access to Control Register 1 and Master Status Register.
A ‘0’ will prevent it.
Keep at ’0’ for normal operation.
The state of this pin will select the mode of the IRQ/NDA pin.
A ’0’ will enable the IRQ pin for HDLC interrupts.
A ’1’ will enable the New Data Available signal which identifies the access time to the
synchronous registers. (If NDA is enabled, the HDLC interrupts are disabled.)
A ’0’ will enable the transmission of the M
Register (refer to Table 13). The selection of M or S is determined by the HALF signal
(refer to functional timing).
A ’1’ will disable this feature forcing the M and S bits to binary zero.
The Parallel/Serial Control bit selects the source of the control channel. If ’0’, then the
C-channel Register is access through the ST-BUS stream. If ’1’, then the C-channel
Register is accessed through the microprocessor port.
Keep at ‘0’ for normal operation.
When set to ‘1’, this bit disables the S-Bus signal receiver. It can be used, for example, to
force INFO4 to INFO2 transition in the NT state machine while receiving INFO3 from the
TE.
Keep at ‘0’ for normal operation.
Table 3. Master Control Register (Read/Write Add. 00000
Table 4. Control Register 1 (Write Add. 10000
DESCRIPTION
DESCRIPTION
(2)
or S bit as selected in the NT Mode C-channel
B
)
B
)
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