MPC9456 Freescale Semiconductor, MPC9456 Datasheet - Page 4

• Manufacturer Part Number: MPC9456
• Description: 2.5V AND 3.3V LVCMOS CLOCK FANOUT BUFFER
• Manufacturer: Freescale Semiconductor

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MPC9456
a.
b.
c.
d.
a.
b.
c.
d.
e.
Table 6: DC Characteristics (V CC = V CCA = V CCB = V CCC = 3.3V
MOTOROLA
Symbol
V CMR a
Table 7: AC Characteristics (V CC = V CCA = V CCB = V CCC = 3.3V
t PLZ, HZ
t PZL, LZ
I CCQ d
Symbol
Z OUT
V CMR c
t P, REF
t sk(PP)
V OH
t SK(P)
V PP
V OL
t sk(O)
V IH
f MAX
V IL
t PLH
t PHL
DC Q
I IN
V PP
t r , t f
t r , t f
f ref
and the input swing lies within the V PP (DC) specification.
Input pull-up / pull-down resistors influence input current.
The MPC9456 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated
transmission line to a termination voltage of V TT . Alternatively, the device drives up to two 50 series terminated transmission lines.
I CCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
AC characteristics apply for parallel output termination of 50 to V TT .
The MPC9456 is functional up to an input and output clock frequency of 350 MHz and is characterized up to 250 MHz.
V CMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V CMR range
and the input swing lies within the V PP (AC) specification.
Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input
pulse width, output duty cycle and maximum frequency specifications.
Output pulse skew is the absolute difference of the propagation delay times: | t pLH - t pHL |.
V CMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V CMR range
Input high voltage
Input low voltage
Peak-to-peak input voltage
Common Mode Range
Input current b
Output High Voltage
Output Low Voltage
Output impedance
Maximum Quiescent Supply Current
Input Frequency
Maximum Output Frequency
Peak-to-peak input voltage
Common Mode Range
Reference Input Pulse Width
PCLK Input Rise/Fall Time
Propagation delay
Output Disable Time
Output Enable Time
Output-to-output Skew
Device-to-device Skew
Output pulse skew e
Output Duty Cycle
Output Rise/Fall Time
Any output bank, same output divider
Characteristics
Characteristics
Any output, Any output divider
Freescale Semiconductor, Inc.
For More Information On This Product,
Within one bank
CCLK to any Q
CCLK to any Q
PCLK
PCLK
1 output
2 output
1 output
2 output
PCLK
PCLK
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Min
-0.3
250
2.0
1.1
2.4
Min
500
1.3
1.4
2.2
2.2
0.1
47
45
0
0
0
4
14 - 17
Typ
5%, T A = –40 to +85 C)
Typ
2.8
2.8
5%, T A = –40 to +85 C) a
50
50
V CC + 0.3
V CC -0.6
Max
0.55
0.30
200
V CC -0.8
0.8
2.0
250 b
250 b
1000
Max
1.0 d
4.45
2.25
125
150
200
350
200
4.2
1.0
10
10
53
55
Unit
mV
mA
W
V
V
V
V
V
V
A
MHz
MHz
MHz
Unit
mV
ns
ns
ns
ns
ns
ns
ps
ps
ps
ns
ps
ns
%
%
V
LVCMOS
LVCMOS
LVPECL
LVPECL
V IN =GND or V IN =V CC
I OH =-24 mA c
I OL = 24mA b
I OL = 12mA
All V CC Pins
FSELx=0
FSELx=1
LVPECL
LVPECL
0.8 to 2.0V
DC REF = 50%
DC REF = 25%-75%
0.55 to 2.4V
TIMING SOLUTIONS
Condition
Condition