ADC1207S080 NXP Semiconductors, ADC1207S080 Datasheet
ADC1207S080
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ADC1207S080 Summary of contents
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... The ADC1207S080 offers the most flexible acquisition control system because of its programmable Complete Conversion Signal (CCS) that allows to adjust the delay of the acquisition clock. The ADC1207S080 offers the lowest input capacitance (< 1 pF) and therefore the highest flexibility in front-end aliasing filter strategy because of its internal front-end buffer. 2. Features ...
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... ADC1207S080 front-end buffer TRACK RESISTOR AND LADDERS HOLD U/I VREF CMADC REFERENCE REFERENCE CMADC DEC Rev. 02 — 7 August 2008 ADC1207S080 www.DataSheet4U.com Sampling frequency Version (MHz) SOT545-2 80 CLK CLKN DEL0 to 2 CLOCK DRIVER DEL1 CCS D11 LATCH ...
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... I complete conversion signal delay input complete conversion signal delay input digital supply voltage 2 (5.0 V) Rev. 02 — 7 August 2008 ADC1207S080 www.DataSheet4U.com ...
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... P analog supply voltage 2 (5 analog supply voltage 1 (5 analog ground analog supply voltage 1 (5 analog ground 1 exposed G digital ground die pad Rev. 02 — 7 August 2008 ADC1207S080 www.DataSheet4U.com © NXP B.V. 2008. All rights reserved ...
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... V and +7.0 V provided that the CCA CCD are respected. CC may have any value between 0.5 V and +5.0 V provided that the supply voltage CCO are respected. CC Thermal characteristics Parameter thermal resistance from junction to ambient thermal resistance from junction to case Rev. 02 — 7 August 2008 ADC1207S080 www.DataSheet4U.com Min Max [1] 0.5 +7.0 [1] 0.5 +7.0 [2] 0.5 +5 ...
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... V [ MHz - clk [ MHz - clk 1. ref(fs) CCA = V 1. ref(fs) CCA [2] 6.3 [ i(IN) i(INN) CCA output code = 2047 DGND 0.7 Rev. 02 — 7 August 2008 ADC1207S080 www.DataSheet4U.com 1.95 V; typical values measured at Typ Max 5.0 5.25 5.0 5.25 3.3 3.6 120 135 840 990 - 3.52 - 0 CCD - 1.5 1 ...
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... CCA = ref(fs DGND 0 CCO output level between 0.1 0.5 V and V CCO 2 Rev. 02 — 7 August 2008 ADC1207S080 www.DataSheet4U.com 1.95 V; typical values measured at Typ Max 0.3 V CCD CCD CCD 1.88 - CCA V 1.95 - CCA V 1.80 - CCA 0 ...
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... MHz - 21.4 MHz - MHz - 175 MHz - i [6] = 21.4 MHz - MHz - 175 MHz - i(IN) i(INN MHz clk Rev. 02 — 7 August 2008 ADC1207S080 www.DataSheet4U.com amb 1.95 V; typical values measured at Typ Max Unit - 9.5 MHz - - MHz 2.0 - LSB 0.6 - LSB +8 +24 mV 2.5 - %FS ...
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... CLK input is at PECL level and sampling is taken on the falling edge of the clock input CCD ) CLKN input is at PECL level and sampling is taken on the rising edge of the clock input CCD i Rev. 02 — 7 August 2008 ADC1207S080 www.DataSheet4U.com amb 1.95 V; typical values measured at Typ Max Unit 67 ...
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... IN sample sample sample Rev. 02 — 7 August 2008 ADC1207S080 www.DataSheet4U.com Two’s complement outputs (D11 to D0) 1000 0000 0000 1000 0000 0000 1000 0000 0001 1111 1111 1111 0111 1111 1110 0111 1111 1111 0111 1111 1111 binary; active two’ ...
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... Fig 4. Single tone; f 2.2 V i(a)(p-p) (V) 2.0 1.8 1.6 1.4 Fig 5. ADC full-scale; V The ADC1207S080 allows modifying the ADC full-scale. This could be done with FSIN (full-scale input) according to ADC1207S080_2 Product data sheet Single 12 bits ADC MHz with direct/ultra high IF sampling 0 (1) (2) ( MHz; 0 dBc 5.1 MHz ...
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... The ADC1207S080 generates an adjustable clock output called Complete Conversion Signal (CCS), which can be used to control the acquisition of converted output data by the digital circuit connected to the ADC1207S080 output data bus. Two logic inputs, DEL0 and DEL1 pins, allow adjusting the delay of the edge of the CCS signal to achieve an optimal position in the stable, usable zone of the data ...
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... Single 12 bits ADC MHz with direct/ultra high IF sampling V i – V ideal i i ----------------------------------------- - S is the input voltage – --------------------------------------- - M/N, with M number of cycles and N number Rev. 02 — 7 August 2008 ADC1207S080 www.DataSheet4U.com 2). SFDR frequency 014aaa437 t © NXP B.V. 2008. All rights reserved ...
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... P noise + distortion SINAD 1.76 – ---------------------------------- 6.02 P harmonics = 10log ------------------------ - 10 P signal signal --------------- - = 10log 10 P noise 1 = 20log ------------------ 10 max S Rev. 02 — 7 August 2008 ADC1207S080 www.DataSheet4U.com is the power of the terms which include the © NXP B.V. 2008. All rights reserved ...
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... Rev. 02 — 7 August 2008 ADC1207S080 www.DataSheet4U.com frequency 014aaa439 – ...
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... NXP Semiconductors 12. Application information 12.1 ADC1207S080 in 3G radio receivers The ADC1207S080 has been proven in many 3G radio receivers with various operating conditions regarding Input Frequency (IF), signal IF bandwidth and sampling frequency. The ADC1207S080 is provided with a maximum analog input signal frequency of 400 MHz. It allows a significant cost-down of the RF front-end, from two mixers to only one, even in multi-carriers architecture ...
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... V CCD 4700_000_S 330 nF 4700_000_S 330 nF LM317MDT IN OUT 4.7 F 470 nF ADJ Rev. 02 — 7 August 2008 ADC1207S080 www.DataSheet4U.com ADT1_1WT 100 n. CCD 2.2 k TL431CPK 100 ...
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... 2.5 scale (1) ( 0.20 7.1 4.6 7.1 4.6 9.1 0.5 0.09 6.9 4.4 6.9 4.4 8.9 REFERENCES JEDEC JEITA MS-026 Rev. 02 — 7 August 2008 ADC1207S080 www.DataSheet4U.com detail ( 9.1 0.75 0.9 1 0.2 0.08 0.08 8.9 0.45 0.6 EUROPEAN ISSUE DATE PROJECTION 03-04-07 04-01-29 © NXP B.V. 2008. All rights reserved. ...
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... Product data sheet Single 12 bits ADC MHz with direct/ultra high IF sampling Data sheet status Change notice Product data sheet - Table 1. Table 5. Figure 10. Figure 11. Product data sheet - Rev. 02 — 7 August 2008 ADC1207S080 www.DataSheet4U.com Supersedes ADC1207S080_1 - © NXP B.V. 2008. All rights reserved ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 02 — 7 August 2008 ADC1207S080 www.DataSheet4U.com © NXP B.V. 2008. All rights reserved ...
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... Effective Number Of Bits (ENOB 11.2.3 Total Harmonic Distortion (THD 11.2.4 Signal-to-Noise ratio (S/ 11.2.5 Spurious Free Dynamic Range (SFDR 11.2.6 IMD2 (IMD3 Application information 12.1 ADC1207S080 in 3G radio receivers . . . . . . . 16 12.2 Application diagram . . . . . . . . . . . . . . . . . . . . 17 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 19 15 Legal information 15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20 15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 15 ...