ADC1413D NXP Semiconductors, ADC1413D Datasheet - Page 19

• Manufacturer Part Number: ADC1413D
• Description: Dual 14-bit ADC
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ADC1413D_SER_4
Preliminary data sheet
13.2.3 Common-mode output voltage (V
13.2.4 Biasing
13.3.1 Drive modes
13.3 Clock input
An 0.1 μF filter capacitor should be connected between on the one hand the pins VCMA
and VCMB and on the other hand ground to ensure a low-noise common-mode output
voltage. When AC-coupled, these pins can be used to set the common-mode reference
for the analog inputs, for instance via a transformer middle point.
The common-mode output voltage, V
common-mode input voltage, V
(pins INAM, INBM, INAP, and INBP) must be between 0.9 V and 2 V for optimal
performance.
The ADC1413D can be driven differentially (SINE, LVPECL or LVDS) with little or no
influence on dynamic performances. It can also be driven by a single-ended LVCMOS
signal connected to pin CLKP (CLKM should be connected to ground via a capacitor).
Fig 15. Reference equivalent schematic
Fig 16. LVCMOS single-ended clock input
a. Rising edge LVCMOS
0.1 μF
VCMA
VCMB
clock input
1.5 V
LVCMOS
All information provided in this document is subject to legal disclaimers.
PACKAGE
Rev. 04 — 23 April 2010
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CLKM
CLKP
I(cm)
ESD
, at the inputs to the sample and hold stage
O(cm)
PARASITICS
I(cm)
ADC1413D series; serial JESD204A interface
, should be set externally to 1.5 V (typical). The
)
b. Falling edge LVCMOS
ADC1413D series
COMMON MODE
REFERENCE
clock input
LVCMOS
ADC CORE
© NXP B.V. 2010. All rights reserved.
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CLKM
CLKP
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