GTLP16617MTDX Fairchild Semiconductor, GTLP16617MTDX Datasheet
GTLP16617MTDX
Specifications of GTLP16617MTDX
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GTLP16617MTDX Summary of contents
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... MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2000 Fairchild Semiconductor Corporation Features Bidirectional interface between GTLP and TTL logic ...
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Pin Descriptions Pin Names Description OEAB A-to-B Output Enable (Active LOW) OEBA B-to-A Output Enable (Active LOW) CEAB A-to-B Clock Enable (Active LOW) CEBA B-to-A Clock Enable (Active LOW) LEAB A-to-B Latch Enable (Transparent HIGH) LEBA B-to-A Latch Enable (Transparent ...
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Logic Diagram 3 www.fairchildsemi.com ...
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Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage ( Outputs 3-STATE Outputs Active (Note 7) 0. Output Sink Current into A Port Output ...
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DC Electrical Characteristics Symbol 3.45V, CCQ Ports V 5.25V, CCQ CCQ GND I CCQ 3.45V ...
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AC Electrical Characteristics Over recommended range of supply voltage and operating free-air temperature for B Port and for A Port Symbol From (Input PLH t PHL t LEAB PLH ...
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Test Circuits and Timing Waveforms Test Circuit for A Outputs C includes probes and jig capacitance. L Voltage Waveforms Pulse Duration (Vm Voltage Waveforms Propagation Delay and Setup and Hold Times (Vm Voltage Waveforms Enable and Disable Times (A Port) ...
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Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide www.fairchildsemi.com Package Number MS56A 8 ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...