MD2241-D128-V3 M-Systems Inc., MD2241-D128-V3 Datasheet - Page 38

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MD2241-D128-V3

Manufacturer Part Number
MD2241-D128-V3
Description
Diskonchip Dimm Plus
Manufacturer
M-Systems Inc.
Datasheet
10.4.2 Write Cycle Timing
38
1. CE# may be asserted any time before or after WE# is asserted. If CE# is asserted after WE#, all timing relative to WE# asserted should be
2. CE# may be negated any time before or after WE# is negated. If CE# is negated before WE#, all timing relative to WE# negated will be
referenced to the time CE# was asserted.
referenced to the time CE# was negated.
A[12:0], BHE#
t
t
t
t
t
HO
SU
REC
HO
Symbol
SU
t
t
t
t
D[15:0]
W
Twcyc
t
HO
SU
HO
SU
(CE0)
(CE0)
(WE)
WE#
(CE1)
(CE1)
OE#
CE#
(WE)
(D)
(D)
(A)
(A)
1
2
t
HO
(CE1)
t
Table 11: Write Cycle Timing Definitions
SU
(A)
OE# or WE#
Address to WE#
WE#
CE#
WE#
CE#
WE#
Preliminary Data Sheet, Rev. 1.2
WE# asserted width (RAM
Figure 15: Write Cycle Timing
t
SU
D to WE#
WE#
(all other addresses)
WE# asserted width
(CE0)
Write Cycle Time
to WE#
to WE#
Description
to Address hold time
to start of next cycle
to CE#
setup time
to D hold time
t
time
HO
(A)
to CE#
setup time
tw(WE)
setup time
or OE#
setup time
hold time
hold
t
SU
(D)
tT
t
HO
WCYC
(CE0)
Min
10
28
46
47
80
20
51
6
6
0
2.7V - 3.6V
t
HO
t
REC
(D)
t
(WE)
SU
Max
(CE1)
DiskOnChip DIMM Plus
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
94-SR-002-08-8L

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