MD5811-d256-MECH M-Systems Inc., MD5811-d256-MECH Datasheet - Page 60

• Manufacturer Part Number: MD5811-d256-MECH
• Description: Mobile Diskonchip P3 Data Sheet
• Manufacturer: M-Systems Inc.

9.3.2
In non-PC architectures, the boot code is executed from a boot ROM, and the drivers are usually
loaded from the storage device.
When using Mobile DiskOnChip P3 as the system boot device, the CPU fetches the first
instructions from the Mobile DiskOnChip P3 Programmable Boot Block, which contains the IPL.
Since in most cases this block cannot hold the entire boot loader, the IPL runs minimum
initialization, after which the Secondary Program Loader (SPL) is copied to RAM from flash. The
remainder of the boot loader code then runs from RAM.
The IPL and SPL are located in a separate (binary) partition on Mobile DiskOnChip P3, and can be
hardware protected if required. .
9.3.3
Platforms that host CPUs that wake up in MultiBurst mode should use Asynchronous Boot mode
when using Mobile DiskOnChip P3 as the system boot device.
During platform initialization, certain CPUs wake up in 32-bit mode and issue instruction fetch
cycles continuously. An XScale CPU, for example, initiates a 16-bit read cycle, but after the first
word is read, it continues to hold CE# and OE# asserted while it increments the address and reads
additional data as a burst. A StrongARM CPU wakes up in 32-bit mode and issues double-word
instruction fetch cycles.
Since Mobile DiskOnChip P3 derives its internal clock signal from the CE#, OE# and WE# inputs,
it cannot distinguish between these burst cycles. To support this type of access, Mobile DiskOnChip
P3 must be set in Asynchronous Boot mode by setting the RAM MODE SELECT byte to 8FH. This
can be done through the Mobile DiskOnChip P3 format utility or by customizing the IPL code. For
more information on the format utility, refer to the DiskOnChip Software Utilities user manual or
the TrueFFS Software Development Kit (SDK) developer guide.
Once in Asynchronous Boot mode, the CPU can fetch its instruction cycles from the Mobile
DiskOnChip P3 Programmable Boot Block. After reading from this block and completing boot,
Mobile DiskOnChip P3 returns to derive its internal clock signal from the CE#, OE# and WE#
inputs. Please refer to Section 11.3 for read timing specifications for Asynchronous Boot mode.
57
Non-PC Architectures
Asynchronous Boot Mode
Data Sheet, Rev. 0.3
Mobile DiskOnChip P3
93-SR-009-8L