BSP-15 Equator Technologies, BSP-15 Datasheet - Page 62

• Manufacturer Part Number: BSP-15
• Description: Broadband Signal Processor
• Manufacturer: Equator Technologies

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6.4 AC Characteristics
6.4.1 PLL reference clock input
6.4.2 SDRAM interface timing
BSP-15 Processor Datasheet
The AC timing specifications listed in this section assume a 20 pF load on all output signals of the
BSP-15 DSP.
Table 6-6 PLL Reference Clock Input Conditions
Correct setup and hold times can be guaranteed through internal delay adjustment, controlled by bits
[30:24] of the synchronizer/clock control register in the BSP-15 DSP’s memory block. The SdMrckDly
and SdMckDly fields control internal delay circuits that affect the timing of signals going to and from
Rise/fall time
Duty cycle
Maximum cycle to cycle jitter
Description
Figure 6.1 SDRAM timing measurement conditions
address, data-out, control
sdclk, sdclk1, sdclk2
sdrtnclk
data-in
2 ns maximum (0.4V to 2.4V)
50% ± 10%
± 200 ps
Value
HWR.BSP15.DS.REV.H
t
ds
t
sdram
t
dh
t
os
t
oh
September 6, 2002