PIC16C72-02/SS Microchip Technology, PIC16C72-02/SS Datasheet - Page 44

• Manufacturer Part Number: PIC16C72-02/SS
• Description: 8-Bit CMOS Microcontrollers with A/D Converter
• Manufacturer: Microchip Technology

PIC16C72 Series
FIGURE 8-5:
DS39016A-page 44
bit7
bit 7:
bit 6:
bit 5:
bit 4:
bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
WCOL
R/W-0
WCOL: Write Collision Detect bit
1 = The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0 = No collision
SSPOV: Receive Overflow Indicator bit
In SPI mode
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of over-
flow, the data in SSPSR is lost. Overflow can only occur in slave mode. The user must read the SSPBUF,
even if only transmitting data, to avoid setting overflow. In master operation, the overflow bit is not set
since each new reception (and transmission) is initiated by writing to the SSPBUF register.
0 = No overflow
In I
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don’t
care" in transmit mode. SSPOV must be cleared in software in either mode.
0 = No overflow
SSPEN: Synchronous Serial Port Enable bit
In SPI mode
1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I
1 = Enables the serial port and configures the SDA and SCL pins as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In both modes, when enabled, these pins must be properly configured as input or output.
CKP: Clock Polarity Select bit
In SPI mode
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch) (Used to ensure data setup time)
0000 = SPI master operation, clock = F
0001 = SPI master operation, clock = F
0010 = SPI master operation, clock = F
0011 = SPI master operation, clock = TMR2 output/2
0100 = SPI slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin
0110 = I
0111 = I
1011 = I
1110 = I
1111 = I
SSPOV
R/W-0
2
2
2
C mode
C mode
C mode
SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h) (PIC16CR72)
2
2
2
2
2
C slave mode, 7-bit address
C slave mode, 10-bit address
C firmware controlled master operation (slave idle)
C slave mode, 7-bit address with start and stop bit interrupts enabled
C slave mode, 10-bit address with start and stop bit interrupts enabled
SSPEN
R/W-0
R/W-0
CKP
SSPM3
R/W-0
Preliminary
OSC
OSC
OSC
SSPM2
R/W-0
/4
/16
/64
SSPM1
R/W-0
SSPM0
R/W-0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
- n =Value at POR reset
1998 Microchip Technology Inc.
read as ‘0’