PIC16C72-02/SS Microchip Technology, PIC16C72-02/SS Datasheet - Page 49
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PIC16C72-02/SS
Manufacturer Part Number
PIC16C72-02/SS
Description
8-Bit CMOS Microcontrollers with A/D Converter
Manufacturer
Microchip Technology
Datasheet
1.PIC16C72-02SS.pdf
(124 pages)
- Current page: 49 of 124
- Download datasheet (2Mb)
8.4.1.2
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
FIGURE 8-8:
SDA
SCL
SSPIF (PIR1<3>)
1998 Microchip Technology Inc.
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
S
RECEPTION
A7 A6 A5 A4 A3 A2 A1
1
2
Receiving Address
I
2
3
C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
4
5
6
7
R/W=0
8
ACK
9
D7
1
D6
2
SSPBUF register is read
Preliminary
Receiving Data
D5
3
Cleared in software
D4
Bit SSPOV is set because the SSPBUF register is still full.
4
D3
5
D2
6
When the address byte overflow condition exists, then
no acknowledge (ACK) pulse is given. An overflow con-
dition is defined as either bit BF (SSPSTAT<0>) is set
or bit SSPOV (SSPCON<6>) is set.
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the byte.
D1
7
D0
8
ACK
9
PIC16C72 Series
D7
1
D6
2
D5
Receiving Data
3
D4
4
ACK is not sent.
D3
5
D2
6
D1
7
D0
DS39016A-page 49
8
ACK
9
Bus Master
terminates
transfer
P
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