74ABT244CMSA Fairchild Semiconductor, 74ABT244CMSA Datasheet
74ABT244CMSA
Manufacturer Part Number
74ABT244CMSA
Description
IC BUFF/DVR TRI-ST DUAL 20SSOP
Manufacturer
Fairchild Semiconductor
Series
74ABTr
Specifications of 74ABT244CMSA
Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
2
Number Of Bits Per Element
4
Current - Output High, Low
32mA, 64mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
74ABT244CMSAX
Manufacturer:
FAIRCHILD
Quantity:
1 204
© 2005 Fairchild Semiconductor Corporation
74ABT244CSC
74ABT244CSJ
74ABT244CMSA
74ABT244CMSAX_NL
(Note 1)
74ABT244CMTC
74ABT244CMTCX_NL
(Note 1)
74ABT244CPC
74ABT244
Octal Buffer/Line Driver with 3-STATE Outputs
General Description
The ABT244 is an octal buffer and line driver with 3-STATE
outputs designed to be employed as a memory and
address driver, clock driver, or bus-oriented transmitter/
receiver.
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Order Number
Package
Number
MSA20
MSA20
MTC20
MTC20
M20B
M20D
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
Pb-Free 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
DS010992
Features
Non-inverting buffers
Output sink capability of 64 mA, source capability of
32 mA
Guaranteed output skew
Guaranteed multiple output switching specifications
Output switching specified for both 50 pF and 250 pF
loads
Guaranteed simultaneous switching, noise level and
dynamic threshold performance
Guaranteed latchup protection
High impedance glitch free bus loading during entire
power up and power down cycle
Nondestructive hot insertion capability
Disable time less than enable time to avoid bus conten-
tion
Package Description
May 1992
Revised March 2005
www.fairchildsemi.com
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