74VCXH16244MTDX Fairchild Semiconductor, 74VCXH16244MTDX Datasheet
![IC BUFF DVR 16BIT LOW V 48TSSOP](/photos/6/92/69261/261-48-tssop_w_sml.jpg)
74VCXH16244MTDX
Specifications of 74VCXH16244MTDX
Related parts for 74VCXH16244MTDX
74VCXH16244MTDX Summary of contents
Page 1
... Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide (Note 2) Note 1: Ordering Code “G” indicates Tray. Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol © 2005 Fairchild Semiconductor Corporation Features 1.2V to 3.6V V supply operation CC 3 ...
Page 2
Connection Diagrams Pin Assignment for TSSOP Pin Assignment for FBGA (Top Thru View) www.fairchildsemi.com Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW –I Bushold Inputs –O Outputs Connect ...
Page 3
Functional Description The 74VCXH16244 contains sixteen non-inverting buffers with 3-STATE outputs. The device is nibble (4 bits) con- trolled with each nibble functioning identically, but indepen- dent of each other. The control pins may be shorted together to obtain full ...
Page 4
Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage ( Outputs 3-STATED Outputs Active (Note 4) 0. Input Diode Current ( ...
Page 5
DC Electrical Characteristics Symbol Parameter V LOW Level Output Voltage OL I Input Leakage Current Control Pins I Data Pins I Bushold Input Minimum I(HOLD) Drive Hold Current I Bushold Input Over-Drive I(OD) Current to Change State I 3-STATE Output ...
Page 6
AC Electrical Characteristics Symbol Parameter t Propagation Delay C PHL t PLH C t Output Enable Time C PZL t PZH C t Output Disable Time C PLZ t PHZ C t Output to Output Skew C OSHL t (Note ...
Page 7
AC Loading and Waveforms (V TEST PLH PHL PZL PLZ PZH PHZ FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE 3. 3-STATE Output High Enable and Disable Times for Low ...
Page 8
AC Loading and Waveforms (V t PLH t PZL t PZH FIGURE 6. Waveform for Inverting and Non-Inverting Functions FIGURE 7. 3-STATE Output High Enable and Disable Times for Low Voltage Logic FIGURE 8. 3-STATE Output Low Enable and Disable ...
Page 9
Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A Preliminary 9 www.fairchildsemi.com ...
Page 10
Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...