ISL22326 Intersil Corporation, ISL22326 Datasheet - Page 10

• Manufacturer Part Number: ISL22326
• Manufacturer: Intersil Corporation

When the device is powered down, the last value stored in
IVRi will be maintained in the non-volatile memory. When
power is restored, the contents of the IVRi are recalled and
loaded into the corresponding WRi to set the wipers to the
initial value.
DCP Description
Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL pins). The RW pin of each DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position
of the wiper terminal within the DCP is controlled by volatile
Wiper Register (WR). Each DCP has its own WR. When the
WR of a DCP contains all zeroes (WR[6:0]= 00h), its wiper
terminal (RW) is closest to its “Low” terminal (RL). When the
WR register of a DCP contains all ones (WR[6:0]= 7Fh), its
wiper terminal (RW) is closest to its “High” terminal (RH). As
the value of the WR increases from all zeroes (0) to all ones
(127 decimal), the wiper moves monotonically from the
position closest to RL to the closest to RH. At the same time,
the resistance between RW and RL increases monotonically,
while the resistance between RH and RW decreases
monotonically.
While the ISL22326 is being powered up, all WRs are reset
to 40h (64 decimal), which locates RW roughly at the center
between RL and RH. After the power supply voltage
becomes large enough for reliable non-volatile memory
reading, all WRs will be reload with the value stored in
corresponding non-volatile Initial Value Registers (IVRs).
The WRs can be read or written to directly using the I
serial interface as described in the following sections. The
I
access the WR of DCP0 or DCP1 respectively.
Memory Description
The ISL22326 contains seven non-volatile and three volatile
8-bit registers. Memory map of ISL22326 is on Table 1. The
two non-volatile registers (IVRi) at address 0 and 1, contain
initial wiper value and volatile registers (WRi) contain current
wiper position. In addition, five non-volatile General Purpose
registers from address 2 to address 6 are available.
2
ADDRESS
C interface Address Byte has to be set to 00h or 01h to
8
7
6
5
4
3
2
1
0
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
NON-VOLATILE
TABLE 1. MEMORY MAP
IVR1
IVR0
—
10
Reserved
Not Available
Not Available
Not Available
Not Available
Not Available
VOLATILE
WR1
WR0
ACR
2
C
ISL22326
The non-volatile IVRi and volatile WRi registers are
accessible with the same address.
The Access Control Register (ACR) contains information
and control bits described below in Table 2. The VOL bit at
access control register (ACR[7]) determines whether the
access is to wiper registers WRi or initial value registers
IVRi.
If VOL bit is 0, the non-volatile IVRi registers are accessible.
If VOL bit is 1, only the volatile WRi are accessible. Note,
value is written to IVRi register also is written to the
corresponding WRi. The default value of this bit is 0.
The SHDN bit (ACR[6]) disables or enables Shutdown
mode. This bit is logically OR’d with SHDN pin. When this bit
is 0, DCP is in Shutdown mode. Default value of SHDN bit
is 1.
The WIP bit (ACR[5]) is read only bit. It indicates that
non-volatile write operation is in progress. It is impossible to
write to the IVRi, WRi or ACR while WIP bit is 1.
I
The ISL22326 supports an I
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is a master and
the device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL22326
operates as a slave device in all applications.
All communication over the I
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line must change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (See
Figure 16). On power-up of the ISL22326 the SDA pin is in
the input mode.
All I
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL22326 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (See
Figure 16). A START condition is ignored during the
power-up of the device.
All I
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (See Figure 16). A STOP condition at the end
of a read operation, or at the end of a write operation places
the device in its standby mode.
2
C Serial Interface
VOL
2
2
C interface operations must begin with a START
C interface operations must be terminated by a STOP
TABLE 2. ACCESS CONTROL REGISTER (ACR)
SHDN
WIP
2
2
C bidirectional bus oriented
0
C interface is conducted by
0
0
0
July 17, 2006
FN6176.0
0