ISL22346 Intersil Corporation, ISL22346 Datasheet - Page 12

no-image

ISL22346

Manufacturer Part Number
ISL22346
Description
Manufacturer
Intersil Corporation
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISL22346UFRT20Z
Manufacturer:
INTERSIL
Quantity:
20 000
Company:
Part Number:
ISL22346UFRT20Z
Quantity:
225
Part Number:
ISL22346UFRT20Z-TK
Manufacturer:
Intersil
Quantity:
800
Part Number:
ISL22346UFV20Z
Manufacturer:
Intersil
Quantity:
652
Part Number:
ISL22346UFV20Z-TK
Manufacturer:
Intersil
Quantity:
950
Part Number:
ISL22346WFV20Z
Manufacturer:
Intersil
Quantity:
666
Part Number:
ISL22346WFVZ
Quantity:
319
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL22346 responds with an ACK. At this time, the device
enters its standby state (See Figure 18). Device can receive
more than one byte of data by auto incrementing the
address after each received byte. Note after reaching the
address 08h, the internal pointer “rolls over” to address 00h.
The non-volatile write cycle starts after STOP condition is
determined and it requires up to 20ms delay for the next
non-volatile write. Thus, non-volatile registers must be
written individually.
SIGNAL AT SDA
FROM THE
SIGNALS
MASTER
SIGNALS FROM
THE SLAVE
S
A
R
T
T
1
IDENTIFICATION
0
BYTE WITH
1
R/W=0
0
A2
12
A1
A0
0
A
C
K
0 0 0
ADDRESS
BYTE
0
FIGURE 19. READ SEQUENCE
A
C
K
ISL22346
A
R
S
T
T
1
IDENTIFICATION
0
BYTE WITH
1
R/W=1
0
A2
Read Operation
A Read operation consist of a three byte instruction followed
by one or more Data Bytes (See Figure 19). The master
initiates the operation issuing the following sequence: a
START, the Identification byte with the R/W bit set to “0”, an
Address Byte, a second START, and a second Identification
byte with the R/W bit set to “1”. After each of the three bytes,
the ISL22346 responds with an ACK. Then the ISL22346
transmits Data Bytes as long as the master responds with an
ACK during the SCL cycle following the eighth bit of each
byte. The master terminates the read operation (issuing a
ACK and a STOP condition) following the last bit of the last
Data Byte (See Figure 19).
The Data Bytes are from the registers indicated by an
internal pointer. This pointer initial value is determined by the
Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 08h, the pointer “rolls
over” to 00h, and the device continues to output data for
each ACK received.
In order to read back the non-volatile IVR, it is recommended
that the application reads the ACR first to verify the WIP bit
is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat
its reading sequence again.
A1
A0
1
A
C
K
FIRST READ
DATA BYTE
A
C
K
A
C
K
LAST READ
DATA BYTE
July 28, 2006
A
C
K
FN6177.0
S
T
O
P

Related parts for ISL22346