PIC16CR58A Microchip Technology, PIC16CR58A Datasheet - Page 13
PIC16CR58A
Manufacturer Part Number
PIC16CR58A
Description
ROM-Based 8-Bit CMOS Microcontroller Series
Manufacturer
Microchip Technology
Datasheets
1.PIC16C61.pdf
(336 pages)
2.PIC16CR58A.pdf
(217 pages)
3.PIC16CR58A.pdf
(217 pages)
4.PIC16C52-04SO.pdf
(218 pages)
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16CR58A-04/P042
Manufacturer:
MOTOROLA
Quantity:
80
- PIC16C61 PDF datasheet
- PIC16CR58A PDF datasheet #2
- PIC16CR58A PDF datasheet #3
- PIC16C52-04SO PDF datasheet #4
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3.1
The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the
program counter is incremented every Q1, and the
instruction is fetched from program memory and
latched into instruction register in Q4. It is decoded
and executed during the following Q1 through Q4. The
clocks and instruction execution flow is shown in
Figure 3-2 and Example 3-1.
FIGURE 3-2:
EXAMPLE 3-1:
1. MOVLW 55H
2. MOVWF PORTB
3. CALL
4. BSF
1998 Microchip Technology Inc.
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
OSC2/CLKOUT
Clocking Scheme/Instruction Cycle
(RC mode)
SUB_1
PORTA, BIT3
OSC1
Q4
PC
Q2
Q3
Q1
CLOCK/INSTRUCTION CYCLE
INSTRUCTION PIPELINE FLOW
Q1
Execute INST (PC-1)
Fetch INST (PC)
Q2
Fetch 1
PC
Q3
Execute 1
Q4
Fetch 2
Preliminary
Q1
Execute INST (PC)
Fetch INST (PC+1)
Execute 2
Q2
Fetch 3
PC+1
3.2
An Instruction Cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO)
then two cycles are required to complete the
instruction (Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is
latched into the Instruction Register (IR) in cycle Q1.
This instruction is then decoded and executed during
the Q2, Q3, and Q4 cycles. Data memory is read
during Q2 (operand read) and written during Q4
(destination write).
Q3
Execute 3
Q4
Fetch 4
Instruction Flow/Pipelining
Q1
Fetch SUB_1 Execute SUB_1
Execute INST (PC+1)
Fetch INST (PC+2)
Q2
Flush
PC+2
PIC16C5X
Q3
Q4
DS30453B-page 13
Internal
phase
clock
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