CM3202-00 California Micro Devices Corporation, CM3202-00 Datasheet - Page 7

• Manufacturer Part Number: CM3202-00
• Description: Ddr Vddq And Termination Voltage Regulator
• Manufacturer: California Micro Devices Corporation

Application Information
Powering DDR Memory
Double-Data-Rate (DDR) memory has provided a huge
step in performance for personal computers, servers
and graphic systems. As is apparent in its name, DDR
operates at double the data rate of earlier RAM, with
two memory accesses per cycle versus one. DDR
SDRAM's transmit data at both the rising falling edges
of the memory bus clock.
DDR’s use of Stub Series Terminated Logic (SSTL)
topology improves noise immunity and power-supply
rejection, while reducing power dissipation. To achieve
this performance improvement, DDR requires more
complex power management architecture than previ-
ous RAM technology.
Unlike the conventional DRAM technology, DDR
SDRAM uses differential inputs and a reference volt-
age for all interface signals. This increases the data
bus bandwidth, and lowers the system power con-
sumption. Power consumption is reduced by lower
operating voltage, a lower signal voltage swing associ-
ated with Stub Series Terminated Logic (SSTL_2) and
by the use of a termination voltage, V
industry standard, defined in JEDEC document
JESD8-9. SSTL_2 maintains high-speed data bus sig-
nal integrity by reducing transmission reflections.
JEDEC further defines the DDR SDRAM specification
in JESD79C.
DDR memory requires three tightly regulated voltages:
V
SSTL_2 receiver, the higher current VDDQ supply volt-
age is normally 2.5V with a tolerance of ±200-mV. The
active bus termination voltage, V
V
1%, and is compared with the V
the receiver. V
© 2006 California Micro Devices Corp. All rights reserved.
08/16/06
DDQ
REF
Figure 1. Typical DDR terminations, Class II
VDDQ
, V
is a reference voltage that tracks half of V
Transmitter
TT
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
, and V
Rs = 25
TT
must be within ±40-mV of V
REF
Line
VREF (=VDDQ/2)
(see
VTT (=VDDQ/2)
Figure
TT
Rt = 25
TT
terminated signal at
, is half of V
TT
1). In a typical
. SSTL_2 is an
VDDQ
REF
Receiver
DDQ
.
DDQ
●
, ±
.
Tel: [phone]
The VTT power requirement is proportional to the num-
ber of data lines and the resistance of the termination
resistor, but does not vary with memory size. In a typi-
cal DDR data bus system each data line termination
may momentarily consume 16.2-mA to achieve the
405-mV minimum over V
A typical 64 Mbyte SSTL-2 memory system, with 128
terminated lines, has a worst-case maximum V
ply current up to ± 2.07A. However, a DDR memory
system is dynamic, and the theoretical peak currents
only occur for short durations, if they ever occur at all.
These high current peaks can be handled by the V
external capacitor. In a real memory system, the con-
tinuous average V
is less than ± 200 mA.
The VDDQ power supply, in addition to supplying cur-
rent to the memory banks, could also supply current to
controllers and other circuitry. The current level typi-
cally stays within a range of 0.5A to 1A, with peaks up
to 2A or more, depending on memory size and the
computing operations being performed.
The tight tracking requirements and the need for V
sink, as well as source, current provide unique chal-
lenges for powering DDR SDRAM.
CM3202 Regulator
The CM3202 dual output linear regulator provides all of
the power requirements of DDR memory by combining
two linear regulators into a single TDFN-8 package.
VDDQ regulator can supply up to 2A current, and the
two-quadrant V
sink and source capability to ±2A. The VDDQ linear
regulator uses a PMOS pass element for a very low
dropout voltage, typically 500mV at a 2A output. The
output voltage of V
age divider. The use of regulators for both the upper
and lower side of the VDDQ output allows a fast tran-
sient response to any change of the load, from high
current to low current or inversely. The second output,
V
divider. Same as VDDQ, VTT has the same fast tran-
sient response to load change in both directions. The
V
TT
TT
I
terminaton
, is regulated at V
regulator can source, as well as sink, up to 2A cur-
=
●
-------------------- -
Rt 25Ω
405mV
(
TT
Fax: [phone]
TT
DDQ
termination regulator has current
)
current level in normal operation
=
can be set by an external volt-
DDQ
16.2mA
TT
needed at the receiver:
/2 by an internal resistor
PRELIMINARY
●
www.cmd.com
CM3202
TT
TT
sup-
TT
to
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