CM3202-02 California Micro Devices Corporation, CM3202-02 Datasheet - Page 8

• Manufacturer Part Number: CM3202-02
• Description: Ddr Vddq And Termination Voltage Regulator
• Manufacturer: California Micro Devices Corporation

Application Info
Powering DDR Memory
Double-Data-Rate (DDR) memory has provided a huge
step in performance for personal computers, servers
and graphic systems. As is apparent in its name, DDR
operates at double the data rate of earlier RAM, with
two memory accesses per cycle versus one. DDR
SDRAMs transmit data at both the rising and falling
edges of the memory bus clock.
DDR’s use of Stub Series Terminated Logic (SSTL)
topology improves noise immunity and power-supply
rejection, while reducing power dissipation. To achieve
this performance improvement, DDR requires more
complex
previous RAM technology.
Unlike the conventional DRAM technology, DDR
SDRAM uses differential inputs and a reference
voltage for all interface signals. This increases the data
bus bandwidth, and lowers the system power
consumption. Power consumption is reduced by lower
operating voltage, a lower signal voltage swing
associated
(SSTL_2), and by the use of a termination voltage, V
SSTL_2 is an industry standard defined in JEDEC
document JESD8-9. SSTL_2 maintains high-speed
data bus signal integrity by reducing transmission
reflections. JEDEC further defines the DDR SDRAM
specification in JESD79C.
DDR memory requires three tightly regulated voltages:
V
SSTL_2 receiver, the higher current V
voltage is normally 2.5V with a tolerance of ±200mV.
The active bus termination voltage, V
V
V
signal at the receiver. V
V
© 2007 California Micro Devices Corp. All rights reserved.
8
DDQ
DDQ
DDQ
REF
Figure 1. Typical DDR terminations, Class II
.
VDDQ
, V
. V
±1%, and is compared with the V
Transmitter
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
REF
TT
power
, and V
Rs = 25
is a reference voltage that tracks half of
with
Stub
management
REF
Line
TT
(see
VREF (=VDDQ/2)
VTT (=VDDQ/2)
Series
must be within ±40-mV of
Figure
Rt = 25
Terminated
architecture
1). In a typical
VDDQ
TT
TT
DDQ
, is half of
terminated
Receiver
supply
Logic
●
than
TT
Tel: [phone]
.
The VTT power requirement is proportional to the
number of data lines and the resistance of the
termination resistor, but does not vary with memory
size. In a typical DDR data bus system each data line
termination may momentarily consume 16.2mA to
achieve the 405mV minimum over V
receiver:
A typical 64Mbyte SSTL-2 memory system, with 128
terminated lines, has a worst-case maximum V
supply current up to ± 2.07A. However, a DDR memory
system is dynamic, and the theoretical peak currents
only occur for short durations, if they ever occur at all.
These high current peaks can be handled by the V
external capacitor. In a real memory system, the
continuous average V
operation is less than ± 200mA.
The VDDQ power supply, in addition to supplying
current to the memory banks, could also supply current
to controllers and other circuitry. The current level
typically stays within a range of 0.5A to 1A, with peaks
up to 2A or more, depending on memory size and the
computing operations being performed.
The tight tracking requirements and the need for V
sink, as well as source, current provide unique
challenges for powering DDR SDRAM.
CM3202-02 Regulator
The CM3202-02 dual output linear regulator provides
all of the power requirements of DDR memory by
combining two linear regulators into a single TDFN-8
package. VDDQ regulator can supply up to 2A current,
and the two-quadrant V
current sink and source capability to ±2A. The VDDQ
linear regulator uses a PMOS pass element for a very
low dropout voltage, typically 500mV at a 2A output.
The output voltage of V
voltage divider. The use of regulators for both the
upper and lower side of the VDDQ output allows a fast
transient response to any change of the load, from high
current to low current or inversely. The second output,
V
divider. Same as VDDQ, VTT has the same fast
transient response to load change in both directions.
The V
TT
I
terminaton
, is regulated at V
TT
regulator can source, as well as sink, up to 2A
=
●
-------------------- -
Rt 25Ω
405mV
Fax: [phone]
(
)
=
DDQ
DDQ
16.2mA
TT
TT
/2 by an internal resistor
current level in normal
termination regulator has
can be set by an external
PRELIMINARY
●
CM3202-02
www.cmd.com
TT
needed at the
05/25/07
TT
TT
TT
to