BC41B143A-ds-003Pc CSR, BC41B143A-ds-003Pc Datasheet - Page 58

• Manufacturer Part Number: BC41B143A-ds-003Pc
• Description: Blue Core ROM Plug-n-Go
• Manufacturer: CSR

10.4.1 UART Bypass
10.4.2 UART Configuration While RESET is Active
The UART interface for BlueCore4-ROM Plug-n-Go while the chip is being held in reset is tri-state. This will allow the
user to daisy chain devices onto the physical UART bus. The constraint on this method is that any devices connected
to this bus must tri-state when BlueCore4-ROM Plug-n-Go reset is de-asserted and the firmware begins to run.
10.4.3 UART Bypass Mode
Alternatively, for devices that do not tri-state the UART bus, the UART bypass mode on BlueCore4-ROM Plug-n-Go
can be used. The default state of BlueCore4-ROM Plug-n-Go after reset is de-asserted; this is for the host UART bus
to be connected to the BlueCore4-ROM Plug-n-Go UART, thereby allowing communication to BlueCore4-ROM
Plug-n-Go via the UART. All UART bypass mode connections are implemented using CMOS technology and have
signalling levels of 0V and VDD_PADS.
In order to apply the UART bypass mode, a BCCMD command will be issued to BlueCore4-ROM Plug-n-Go. Upon
this issue, it will switch the bypass to PIO[7:4] as Figure 10.12 indicates. Once the bypass mode has been invoked,
BlueCore4-ROM Plug-n-Go will enter the Deep Sleep state indefinitely.
In order to re-establish communication with BlueCore4-ROM Plug-n-Go, the chip must be reset so that the default
configuration takes effect.
It is important for the host to ensure a clean Bluetooth disconnection of any active links before the bypass mode is
invoked. Therefore, it is not possible to have active Bluetooth links while operating the bypass mode.
10.4.4 Current Consumption in UART Bypass Mode
The current consumption for a device in UART bypass mode is equal to the values quoted for a device in standby
mode.
BC41B143A-ds-003Pc
(1)
The range of the signalling level for the standard UART described in section 10.4 and the UART bypass may differ between CSR BlueCore
devices, as the power supply configurations are chip dependent. For BlueCore4-ROM Plug-n-Go, the standard UART is supplied by
VDD_USB, so has signalling levels of 0V and VDD_USB. Whereas in the UART bypass mode, the signals appear on PIO[4:7] which are
supplied by VDD_PADS, therefore the signalling levels are 0V and VDD_PADS.
Host Processor
RXD
CTS
RTS
TXD
Test Interface
Figure 10.12: UART Bypass Architecture
(1)
© Cambridge Silicon Radio Limited 2005
UART_TX
UART_RTS
UART_CTS
UART_RX
RESET
Advance Information
BlueCore
UART
PIO4
PIO5
PIO6
PIO7
Another Device
TX
RTS
CTS
RX
Device Terminal Descriptions
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