AN178 Philips, AN178 Datasheet - Page 10

• Manufacturer Part Number: AN178
• Description: Modeling the PLL
• Manufacturer: Philips

DataSheet4U.com
www.DataSheet4U.com
DataSheet
receives I
Philips Semiconductors
PLL BUILDING BLOCKS VCO
Since three different forms of VCO have been used in the Philips
Semiconductors PLL series, the VCO details will not be discussed
until the individual loops are described. However, a few general
comments about VCOs are in order.
When the PLL is locked to a signal, the VCO voltage is a function of
the frequency of the input signal. Since the VCO control voltage is
the demodulated output during FM demodulation, it is important that
the VCO voltage-to-frequency characteristic be linear so that the
output is not distorted. Over the linear range of the VCO, the
conversin gain is given by K
Since the loop output voltage is the VCO voltage, we can get the
loop output voltage as
The gain K
voltage is changed, the frequency change is virtually instantaneous.
Phase Comparator
All of Philips Semiconductors analog phase-locked loops use the
same form of phase comparator — often called the doubly-balanced
multiplier or mixer. Such a circuit is shown in Figure 12.
The input stage formed by transistors Q1 and Q2 may be viewed as
a differential amplifier which has an equivalent collector resistance
R
dynamic emitter resistance, r
where I
The switching stage formed by Q3 – Q6 is switched on and off by
the VCO square wave. Since the collector current swing of Q2 is
the negative of the collector current swing of Q1, the switching
action has the effect of multiplying the differential stage output first
by +1 and then by –1. That is, when the base of Q4 is positive, R
1988 Dec
4
C
U
Modeling the PLL
and whose differential gain at balance is the ratio of R
K
A
.com
O
V
d
E
d
Figure 12. Integrated Phase Comparator Circuit
is the total DC bias current for the differential amplifier pair.
1
O
and when the base of Q6 is positive, R
R
r
can be found from the data sheet. When the VCO
e
C
V
K
O
d
O
O
0.026
I
E
R
C
2
O
0.052
e
R
, of Q1 and Q2.
(in radian/V-sec)
C
I
E
C2
receives i
C
to the
SL01022
DataSheet4U.com
2
(56)
(57)
(58)
= i
C2
1
.
10
Since the circuit is called a multiplier, performing the multiplication
will gain further insight into the action of the phase comparator.
Consider an input signal which consists of two added components: a
component at frequency
frequency and a component at frequency
frequency. The input signal is
where
unity square wave developed in the multiplier by the VCO signal is
where
the appropriate trigonometric relationships, and inserting the
differential stage gain A
Assuming that temporarily V
term (n = 0) has a low frequency difference frequency component.
This is the beat frequency component that feeds around the loop
and causes lock-up by modulating the VCO. As
to
frequency until
becomes
which is the usual phase comparator formula showing the DC
component of the phase comparator during lock. This component
must equal the voltage necessary to keep the VCO at
possible for
and, yet, for the phase to be incorrect so that
without lock being achieved. This explains why lock is usually not
achieved instantaneously, even when
If n
giving the DC phase comparator component
showing that the loop can lock to odd harmonics of the free-running
frequency. The (2n + 1) term in the denominator shows that the
phase comparator’s output is lower for harmonic lock, which
explains why the lock range decreases as higher and higher odd
harmonics are used to achieve lock.
Note also that the phase comparator’s output during lock is
(assuming A
I
v
v
v
[
–
, this difference component becomes lower and lower in
V
V
0 in the first term, the loop can lock when
i
o
e
(t)
n
e
e
(t)
(t)
n
(t)
(t)
i
n
n
O
and
is the VCO frequency. Multiplying the two terms, using
0
d
v
0
n
2A
(2n
0
0
V
O
V
k
is constant) also a function of the input amplitude V
(2n
k
(t)
(2n
(2n
E
E
to equal
are the phase in relation to the VCO signal. The
d
O
V
DataSheet4U.com
V
V
=
I
V
0
k
k
I
1)
V
1)
I
(2n
(2n
1)
1)
I
(2n
d
cos[(2n
and lock is achieved. The first term then
2A
2A
sin(
cos[(2n
gives:
cos[(2n
cos[(2n
I
I
d
d
4
momentarily during the lock-up process
which is close to the free-running
V
V
k
I
I
i
t
is zero, if
1)
1)
1)
cos
cos
sin[(2n
1)
i
1)
)
1)
1)
i
i
I
O
O
=
I
v
t
O
O
t
is close to
k
t
t
K
sin(
O
which may be at any
1)
at t=0.
O
I
t
I
o
I
k
t
passes through
I
I
t
t]
t
t
= (2n + 1)
O
is driven closer
Application note
AN178
i
O
]
i
] ]
, the first
O
i
i
k
]
]
. It is
)
O
,
(59)
(60)
(61)
(62)
(63)
l
.
I