AN178 Philips, AN178 Datasheet - Page 8

• Manufacturer Part Number: AN178
• Description: Modeling the PLL
• Manufacturer: Philips

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Philips Semiconductors
Figure 7 shows the typical frequency-to-voltage transfer
characteristics of the PLL. The input is assumed to be a sine wave
whose frequency is swept slowly over a broad frequency range.
The vertical scale is the corresponding loop error voltage. In Figure
7a, the input frequency is being gradually increased. The loop does
not respond to the signal until it reaches a frequency
corresponding to the lower edge of the capture range. Then, the
loop suddenly locks on the input and causes a negative jump of the
loop error voltage. Next, V
to the reciprocal of VCO conversion gain (1/Ko) and goes through
zero as
reaches
PLL then loses lock and the error voltage drops to zero. If the input
frequency is swept slowly back, the cycle repeats itself, but is
inverted, as shown in Figure 7b. The loop recaptures the signal at
the system are:
and
Note that, as indicated by the transfer characteristics of Figure 7, the
PLL system has an inherent selectivity about the free-running
frequency,
that are separated from
whether the loop starts with or without an initial lock condition. The
linearity of the frequency-to-voltage conversion characteristics for
the PLL is determined solely by the VCO conversion gain.
Therefore, in most PLL applications, the VCO is required to have a
highly linear voltage-to-frequency transfer characteristic.
DETERMINING LOOP RESPONSE
The transient response of a PLL can be calculated using the model
of Figure 4 and Equations 18 and 19 as starting points. Combining
these equations gives
The phase error which keeps the system in lock is
Define a phase error transfer function
As an example of the utilization of these equations, consider the
most common case of a loop employing a simple first-order lag filter
where
For this filter, Equations 29 and 31 become
1988 Dec
4
3
U
Modeling the PLL
and tracks it down to
2
2
H(s)
E(s)
F(s)
H(s)
E(s)
.com
e
(s)
C
L
I
2
=
, corresponding to the upper edge of the lock range. The
O
1
s
S
’. It will respond only to the input signal frequencies
O
e
2
i
o
3
i
(s)
(s)
i
(s)
’. The loop tracks the input until the input frequency
(s)
(s)
1
s(s
s
s
s
K
1
4
1
V
1
1
1
s
o
1
(s)
1
O
K
4
d
’ by less than
. The total capture and lock ranges of
K
V
K
1
varies with frequency with a slope equal
F(s)
K
)
V
V
o
i
V
(s)
(s)
F(s)
1
1
1
C
H(s)
or
L
, depending on
1
,
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8
Both equations are second-order and have the same denominator
which can be expressed as
Where
frequency and damping factor defined as
The system is considered overdamped for > 1.0, and critically
damped = 1.0. Now examine this PLL system’s response to
various types of inputs.
Step-of-Phase Input
Consider a unit step-of-phase as the input signal. This input is
shown in Figure 8 and can be thought of as simply shifting the time
axis by a unit step (one radian or one degree, depending upon the
working units) while maintaining the same input frequency.
Mathematically this input has the form
The phase of VCO output and the system’s phase error are
represented by
(depending upon the working units) while maintaining the same
input frequency. Mathematically this input has the form
and
When = 1, these phase responses are
and
Figure 8. Input Signal Representing a Unit Step of Phase at
D(s)
where
i
o
o
o
e
o
e
n
(s)
(s)
(s)
(t)
(t)
(t)
(t)
1.
n
K
and are, respectively, the system’s undamped natural
1
V 1
s
K
1
s
1
e
1
(1
H(s)
E(s)
2
V
1
s
s
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1
arc tan
e
(1
2K
s
1
n
2
n
n
(t)
t)e
V
1
s
Constant Frequency
s(s
2
sin(
n
2
2
1
n
t
t)e
s
K
sin (
2
V
n
n
2
t 1
t
2
1
n
2
n
s
2
n
n
s
t 1
n
n
t
s
2
2
n
2
n
2
2
2
n
s
Application note
AN178
2
n
SL01018
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