S-1167 Seiko Instruments, S-1167 Datasheet - Page 13
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S-1167
Manufacturer Part Number
S-1167
Description
HIGH RIPPLE REJECTION AND LOW DROPOUT CMOS VOLTAGE REGULATOR
Manufacturer
Seiko Instruments
Datasheet
1.S-1167.pdf
(31 pages)
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www.datasheet4u.com
Rev.2.3
Operation
1. Basic Operation
2. Output Transistor
ULTRA LOW CURRENT CONSUMPTION, HIGH RIPPLE REJECTION AND LOW DROPOUT CMOS VOLTAGE REGULATOR
Figure 12 shows the block diagram of the S-1167 Series.
The error amplifier compares the reference voltage (V
feedback resistors R
output voltage free of any fluctuations of input voltage and temperature.
The S-1167 Series uses a low on-resistance P-channel MOS FET as the output transistor.
Be sure that V
current flowing from the VOUT pin through a parasitic diode to the VIN pin.
_00
OUT
Current supply
*1. Parasitic diode
does not exceed V
VIN
VSS
s
and R
Reference voltage
V
f
. It supplies the output transistor with the gate voltage necessary to ensure a certain
ref
circuit
IN
+ 0.3 V to prevent the voltage regulator from being damaged due to inverse
Error amplifier
Seiko Instruments Inc.
−
+
Figure 12
ref
) with V
fb
, which is the output voltage resistance-divided by
V
R
R
fb
f
s
*1
S-1167 Series
VOUT
13