S-1721 Seiko Instruments, S-1721 Datasheet - Page 15

• Manufacturer Part Number: S-1721
• Description: SUPER-SMALL PACKAGE 2-CIRCUIT HIGH RIPPLE-REJECTION LOW CURRENT CONSUMPTION LOW DROPOUT CMOS VOLTAGE REGULATOR
• Manufacturer: Seiko Instruments

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Rev.1.1
Standard Circuit
Condition of Application
Selection of Input and Output Capacitors (C
The S-1721 Series requires an output capacitor between the VOUT and VSS pin for phase compensation. Operation is
stabilized by a ceramic capacitor with an output capacitance of 1.0 µF or more over the entire temperature range.
When using an OS capacitor, tantalum capacitor, or aluminum electrolytic capacitor, the capacitance must be 1.0 µF or
more.
The value of the output overshoot or undershoot transient response varies depending on the value of the output
capacitor. The required capacitance of the input capacitor differs depending on the application.
The recommended capacitance for an application is C
the output capacitor, perform sufficient evaluation, including evaluation of temperature characteristics, on the actual
device.
Caution
Input capacitor (C
Output capacitor (C
Caution A general series regulator may oscillate, depending on the external components. Confirm that no
SUPER-SMALL PACKAGE 2-CIRCUIT HIGH RIPPLE-REJECTION LOW CURRENT CONSUMPTION LOW DROPOUT CMOS VOLTAGE REGULATOR
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oscillation occurs in the application for which the above capacitors are used.
The above connection diagram and constant will not guarantee successful operation. Perform
thorough evaluation using the actual application to set the constant.
IN
) :
L1
, C
INPUT
*1. C
*2. A ceramic capacitor of 1.0 µF or more can be used for C
C
L2
IN
) :
*1
IN
is a capacitor for stabilizing the input.
1.0 µF or more
1.0 µF or more (ceramic capacitor)
Single GND
VIN
ON/OFF1
ON/OFF2
VSS
Seiko Instruments Inc.
VOUT1
VOUT2
Figure 21
IN
C
L2
≥ 1.0 µF, C
*2
IN
, C
L1
OUTPUT 2
OUTPUT 1
L1
C
GND
, C
L1
≥ 1.0 µF, C
*2
L2
)
L2
L1
≥ 1.0 µF; however, when selecting
and C
L2.
S-1721 Series
15