FM28V010 Ramtron Corporation, FM28V010 Datasheet - Page 5

• Manufacturer Part Number: FM28V010
• Description: 128kbit Bytewide F-ram Memory Features
• Manufacturer: Ramtron Corporation

chip enable must remain inactive for at least the
minimum precharge time t
Precharge is also activated by changing the upper
addess A(13:3). The current row is first closed prior
to accessing the new row. The device automatically
detects an upper order address change which starts a
precharge operation, the new address is latched, and
Endurance
The FM28V010 is capable of being accessed at least
10
operates with a read and restore mechanism.
Therefore, an endurance cycle is applied on a row
basis. The F-RAM architecture is based on an array
of rows and columns. Rows are defined by A13-A3
and column addresses by A2-A0. The array is
organized as 2K rows of 8-bytes each. The entire row
is internally accessed once whether a single byte or
all eight bytes are read or written. Each byte in the
row is counted only once in an endurance calculation
if the addressing is contiguous in nature.
Rev. 1.0
Oct. 2010
14
times – reads or writes. An F-RAM memory
Table 1. Time to Reach 100 Trillion Cycles for Repeating 256-byte Loop
Bus Freq
(MHz)
33
25
10
5
PC
.
Bus Cycle
Time (ns)
100
200
30
40
Transaction
Time (µ µ µ µ s)
256-byte
10.56
12.8
28.8
57.6
Endurance
Cycles/sec.
94,690
78,125
34,720
17,360
the new read data is valid within the t
access time. Refer to the Read Cycle Timing 1
diagram on page 9. Likewise a similar sequence
occurs for write cycles. Refer to the Write Cycle
Timing 3 diagram on page 11. The rate at which
random addresses can be issued is t
respectively.
The user may choose to store CPU instructions and
run them from a certain address space. The table
below shows endurance calculations for 256-byte
repeating loop, which includes a starting address, 7
page mode accesses, and a CE precharge. The
number of bus clocks needed to complete an 8-byte
read transaction is 8+1 at lower bus speeds, but 9+2
at 33MHz due to initial read latency and an extra
clock to satisfy the device’s precharge timing
constraint t
experience only one endurance cycle. F-RAM read
and write endurance is virtually unlimited even at
33MHz system bus clock rate.
Cycles/year
Endurance
2.98 x 10
2.46 x 10
1.09 x 10
5.47 x 10
PC
. The entire loop causes each byte to
12
12
12
11
FM28V010 - 16Kx8 F-RAM
Reach 10
Years to
Cycles
182.8
33.5
40.6
91.7
14
RC
AA
and t
Page 5 of 13
address
WC
,