fm3316 Ramtron Corporation, fm3316 Datasheet
fm3316
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fm3316 Summary of contents
Page 1
... Seconds through Centuries in BCD format Tracks Leap Years through 2099 Uses Standard 32.768 kHz Crystal Software Calibration Supports Battery or Capacitor Backup Description The FM33256 and FM3316 are devices that integrate F-RAM memory with the most commonly needed functions for processor-based systems. ...
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... Backup supply voltage battery or a large value capacitor backup supply is used, this pin should be tied to V VDD Supply Supply Voltage. VSS Supply Ground Rev. 1.1 Dec. 2007 FM33256/FM3316 SPI Companion w/ FRAM Pin Name /CS SCK VDD SI SO ACS PFI SCK PFO ...
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... Operating Configuration Size Voltage FM33256 256Kb 2.7-3.6V FM3316 16Kb 2.7-3.6V Other memory configurations may be available. Please contact the factory for more information. Rev. 1.1 Dec. 2007 FM33256/FM3316 SPI Companion w/ FRAM Special Manual Reset Function Watchdog Registers LV Detect S/N RTC Cal. 1.5V Event Counter Switched Power Battery Backed NV/BB User Programmable Figure 1 ...
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... The companion includes a low-V reset, a programmable watchdog DD Rev. 1.1 Dec. 2007 FM33256/FM3316 SPI Companion w/ FRAM timer, a 16-bit nonvolatile event counter, a comparator for early power-fail detection or other purposes, and a 64-bit serial number. Processor Supervisor Supervisors provide a host processor two basic ...
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... The nonvolatile enable bit WDE allows the /RST to go Rev. 1.1 Dec. 2007 FM33256/FM3316 SPI Companion w/ FRAM active if the watchdog reaches the timeout without being restarted reset occurs, the timer will restart on the rising edge of the reset pulse. If WDE is not ...
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... The counter polarity control bit is CP, register 0Dh bit 0. When the counter increments on a falling edge of CNT, and when CP is set to 1, the Rev. 1.1 Dec. 2007 FM33256/FM3316 SPI Companion w/ FRAM counter increments on a rising edge of CNT. The polarity bit CP is nonvolatile. CNT most ...
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... Since a match will occur for only one value per minute, the Rev. 1.1 Dec. 2007 FM33256/FM3316 SPI Companion w/ FRAM alarm occurs once per minute. Likewise setting the seconds and minutes match select bits causes an exact match of these values. Thus, an alarm will occur once per hour ...
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... Years Months CF 8 bits 5 bits Figure 9. Real-time Clock Core Block Diagram Rev. 1.1 Dec. 2007 FM33256/FM3316 SPI Companion w/ FRAM Months Alarm condition 1 No match required = alarm 1/second 1 Alarm when seconds match = alarm 1/minute 1 Alarm when seconds, minutes match = alarm 1/hour 1 ...
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... CALS = 0. After calibration, the clock will have a maximum error of 2.17 ppm or per month at the calibrated temperature. Rev. 1.1 Dec. 2007 FM33256/FM3316 SPI Companion w/ FRAM The user will not be able to see the effect of the calibration setting on the 512 Hz output. addition or subtraction of digital pulses occurs after the 512 Hz output. , the RTC ...
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... Measured Frequency Range Min Max 0 512.0000 512.0011 1 512.0011 512.0033 Rev. 1.1 Dec. 2007 FM33256/FM3316 SPI Companion w/ FRAM layer, green is the bottom layer. Layout for Through Hole Crystal (red = top layer, green = bottom layer) 2.17 PPM after calibration Error Range (PPM) Min Max Program Calibration Register to: 0 2.17 2 ...
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... Rev. 1.1 Dec. 2007 FM33256/FM3316 SPI Companion w/ FRAM 6.52 10.85 10.86 15.19 15.20 19.53 19.54 23.87 23.88 28.21 28.22 32.55 32.56 36.89 36.90 41.23 41.24 45.57 45.58 49.91 49.92 54.25 54.26 58.59 58.60 62.93 62.94 67.27 67.28 71.61 71.62 75.95 75.96 80.29 80.30 84.63 84.64 88.97 88.98 93.31 93.32 97.65 97.66 101.99 102.00 106.33 106.34 110 ...
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... Rev. 1.1 Dec. 2007 FM33256/FM3316 SPI Companion w/ FRAM BB/NV User Programmable = Alarm months date Alarm date Alarm hours Alarm minutes Alarm seconds F0 VBC FC VTP1 Serial Number Byte 7 ...
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... VTP Select. These bits control the reset trip point for the low-V selected V voltage, the reset pin /RST will drive low and the SPI interface will be locked out. Nonvolatile, TP read/write. Rev. 1.1 Dec. 2007 FM33256/FM3316 SPI Companion w/ FRAM Month Month.3 ...
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... POLL Polled Mode: When POLL=1, the CNT pin is sampled for 30µs every 125ms. If POLL is set, the NVC bit is internally cleared and the CP bit is set to detect a rising edge. The RTC oscillator must be enabled (/OSCEN=0) Rev. 1.1 Dec. 2007 FM33256/FM3316 SPI Companion w/ FRAM SN.61 SN ...
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... WR(3:0) Watchdog Restart. Writing a pattern 1010b to WR(3:0) restarts the watchdog timer. The upper nibble contents do not affect this operation. Writing any pattern other than 1010b to WR3-0 has no effect on the watchdog. Write-only. Rev. 1.1 Dec. 2007 FM33256/FM3316 SPI Companion w/ FRAM WDET4 WDET3 WDET4 WDET3 WDET2 WDET1 WDET0 ...
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... Contains the BCD value of minutes. Lower nibble contains the lower digit and operates from upper nibble contains the upper minutes digit and operates from The range for the register is 0-59. Battery-backed, read/write. Rev. 1.1 Dec. 2007 FM33256/FM3316 SPI Companion w/ FRAM POR ...
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... The user can then read them without concerns over changing values causing system errors. The R bit going from causes the timekeeping capture, so the bit must be returned to 0 prior to reading again. Battery- backed, read/write. Reserved Reserved bits. Do not use. Should remain set to 0. Rev. 1.1 Dec. 2007 FM33256/FM3316 SPI Companion w/ FRAM sec.1 10 sec.0 Seconds.3 ...
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... The SPI interface is a synchronous serial interface using clock and data pins intended to support Rev. 1.1 Dec. 2007 FM33256/FM3316 SPI Companion w/ FRAM multiple devices on the bus. Each device is activated using a chip select. Once chip select is activated by the bus master, the FM33xx will begin monitoring the clock and data lines ...
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... SCK Rev. 1.1 Dec. 2007 FM33256/FM3316 SPI Companion w/ FRAM operation. Sending the WREN op-code will allow the user to issue subsequent op-codes for write operations. These include writing the Status Register, writing the Processor Companion, and writing the memory. Sending the WREN op-code causes the internal Write Enable Latch to be set ...
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... SO Hi-Z Rev. 1.1 Dec. 2007 FM33256/FM3316 SPI Companion w/ FRAM WRSR – Write Status Register The WRSR command allows the user to select certain write protection features by writing a byte to the Status Register. Prior to sending the WRSR command, the user must send a WREN command to enable writes. Note that executing a WRSR command is a write operation and therefore clears the Write Enable Latch ...
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... Upper ¼ Upper ½ All The BP1 and BP0 bits and the Write Enable Latch are the only mechanisms that protect the memory from writes. Rev. 1.1 Dec. 2007 FM33256/FM3316 SPI Companion w/ FRAM Register Address ...
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... Part # 1 FM33256 x A14 A13 FM3316 Rev. 1.1 Dec. 2007 FM33256/FM3316 SPI Companion w/ FRAM If the last address is reached (e.g. 7FFFh on the FM33256), the counter will roll over to 0000h. Data is read MSB first. The rising edge of /CS terminates a READ operation. Figure 20 ...
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... Input High Voltage IH All inputs except as listed below CNT battery-backed (V CNT V > PFI Rev. 1.1 Dec. 2007 FM33256/FM3316 SPI Companion w/ FRAM Description SS SS (JEDEC Std JESD22-A114-E) (JEDEC Std JESD22-C101-C) (JEDEC Std JESD22-A115-A) = 2.7V to 3.6V unless otherwise specified) DD Min 2.7 2.0 =0V BAK 50 200 2 ...
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... WDST t Watchdog EndTime WDET f Frequency of Event Counter CNT Notes 1 This parameter is characterized but not tested. 2 Slope measured at any point Rev. 1.1 Dec. 2007 FM33256/FM3316 SPI Companion w/ FRAM ( 2.7V to 3.6V unless otherwise specified Min = – 0 1.475 ...
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... These diagrams illustrate the timing parameters only. Serial Data Bus Timing CSU SCK Rev. 1.1 Dec. 2007 FM33256/FM3316 SPI Companion w/ FRAM is the programmed EndTime in registers 0Bh and 0Ch, V DOG2 = 3.0V) DD Typ 25 Min Units 10 Years 10% and 90 0.5 V ...
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... Timing VDD VTP VRST RST Rev. 1.1 Dec. 2007 FM33256/FM3316 SPI Companion w/ FRAM RNR t RPU Page ...
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... Legend: XXXXXXX-P LLLLLLL RIC YYWW Example: FM33256, “Green” SOIC package, Year 2006, Work Week 14 Rev. 1.1 Dec. 2007 FM33256/FM3316 SPI Companion w/ FRAM XXXX= part number, P= package type (-G) LLLLLLL= lot code RIC=Ramtron Int’l Corp, YY=year, WW=work week FM33256-G1 A70012G RIC 0714 ...
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... Revision History Revision Date 1.0 12/18/2006 1.1 12/12/2007 Rev. 1.1 Dec. 2007 FM33256/FM3316 SPI Companion w/ FRAM Summary Initial release. Changed I and I spec limits. Added text that Event Counter does not QWD BAKTC roll over. Added suggestion to clear VBC bit when Vbak is not used. Added ESD and package MSL ratings ...