FM6124 Ramtron Corporation, FM6124 Datasheet - Page 18

• Manufacturer Part Number: FM6124
• Description: Event Data Recorder With F-ram
• Manufacturer: Ramtron Corporation

RSTB and RESET input pins
The FM6124 features an active-low RESET input pin.
Applying a manual reset or a power-up Reset of the
FM6124 will clear the volatile registers. However this will
have no impact on the Event buffer content, their
associated pointers, or the MCU companion registers.
The RESET pin features an internal pull-up resistor so if
the reset pin in not used, it can be left unconnected.
Event Deletion
Events are not actually deleted until the circular buffer is
overwritten with new data. Pointers are moved to
effectively prevent access to automatically discarded data.
A pointer move is the last thing done when an event is
popped off of the buffer.
Safety provisions
To prevent data loss or corruption while Events are being
read with the KEEP bit set to 0, Event Read Pointer is only
moved at the following times:
The recording of the event data in the F-RAM Event buffer
memory require ~100µS per event.
simultaneous events occurring on all 12 input of the
FM6124, a total of 12 x 100µS = 1.2ms will be required
for the recording of all event Data. During that period of
time, event can still be registered, but the Event content
will be held into volatile registers.
If the supply voltage is lost before the completion of all
events data transfer into F-RAM memory, the events that
are still in volatile register will be lost. The device will
resume normal operation when the supply comes back.
Pin Snapshot
It is possible to see the state of any pin at any time. Write 1
to the SNAP bit to capture the state of all pins. This bit
will be automatically cleared (Write-Only).
Rev. 4.0 (EOL)
July 2010
•
•
•
After all of the data of an event has been stored
After the 8
steaming Events
As soon as 1 byte is written over the oldest Event,
when recording an Event in a full buffer condition
th
data byte is transmitted when
In the case of
Error Conditions
In situations where an error condition can occur, data sent
back will be 0xFF. This includes reading illegal addresses
and requesting more events and the buffer currently holds.
The ERR bit will be set to 1 and Event registers will be set
to 0xFF until Control Buffer is written.
Output Interrupt: INT pin
The INT pin is an active low output that will react on:
The setting of the “Gen. INT pulse on Pin Event” registers
and resulting activity on INT pin is independent of
corresponding event recording activation.
MCU Companion
The FM6124 includes a real-time clock (RTC) with alarm
and a processor companion along with the EDR serial
nonvolatile F-RAM. The companion is a highly integrated
peripheral including a low-V
watchdog timer, a 16-bit nonvolatile event counter, a
comparator for early power-fail detection or other
purposes, and a 64-bit serial number.
The real-time clock and supervisor functions are accessed
under their own commands. The RTC/alarm and some
control registers are maintained by the power source on the
VBAK pin, allowing them to operate from battery or
backup capacitor power when V
threshold.
Processor Supervisor
Supervisors provide a host processor two basic functions:
Detection of power supply fault conditions and a watchdog
timer to escape a software lockup condition. The FM6124
device has a reset pin (RSTB) to drive a processor reset
input during power faults, power-up, and software lockups.
It is an open drain output with a weak internal pull-up to
V
the RSTB pin. When V
point, RSTB output is pulled weakly to V
below the reset trip point voltage level (V
pin will be driven low. It will remain low until V
too low for circuit operation which is the V
V
for at least 50 ms (t
reliable V
will return to the weak high state. While RSTB is asserted,
serial bus activity is locked out even if a transaction
DD
DD
. This allows other reset sources to be wire-OR’d to
rises again above V
• Any event occurring on any input pin for which
• Full Buffer condition.
DD
the corresponding bit of the “Gen. INT pulse on
Pin Event” Registers have been set to 1.
level. After t
RPU
) to ensure a robust system reset at a
DD
TP
RPU
, RSTB continues to drive low
is above the programmed trip
has been met, the RSTB pin
DD
reset, a programmable
DD
drops below a set
Page 18 of 53
DD
RST
TP
. If V
), the RSTB
level. When
DD
DD
drops
falls