S-24C01A Seiko Instruments Inc, S-24C01A Datasheet - Page 14

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S-24C01A

Manufacturer Part Number
S-24C01A
Description
CMOS 2-WIRE SERIAL EEPROM
Manufacturer
Seiko Instruments Inc
Datasheet

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CMOS 2-WIRED SERIAL EEPROM
S-24C01A/02A/04A
14
8. Address Increment Timing
SCL
SDA
SCL
SDA
The address increment timing is as follows. See Figures 15 and 16. During reading operation, the memory
address counter is automatically incremented at the falling edge of the SCL clock (the 8th read data is
output).
During writing operation, the memory address counter is also automatically incremented at the falling
edge of the SCL clock when the 8th bit write data is fetched.
Purchase of I
Patent Rights to use these components in an I
I
Please note that any product or system incorporating this IC may infringe upon the Philips I
Patent Rights depending upon its configuration.
In the event that such product or system incorporating the I
Rights, Seiko Instruments Inc. shall not bear any responsibility for any matters with regard to and
arising from such patent infringement.
2
C Standard Specification as defined by Philips.
2
R / W=1
R / W=0
C components of Seiko Instruments Inc. conveys a license under the Philips I
8
8
Figure 15 Address Increment Timing During Reading
Figure 16
ACK Output
ACK Output
9
9
Address Increment Timing During Writing
Seiko Instruments Inc.
D7 Output
D7 Input
1
1
2
C system, provided that the system conforms to the
2
C Bus infringes upon the Philips Patent
Address Increment
D0 Output
Address Increment
D0 Input
8
8
ACK Output
9
9
Rev. 2.2
2
2
C Bus
C
_30

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