XC2C64 Xilinx, XC2C64 Datasheet - Page 12

• Manufacturer Part Number: XC2C64
• Description: (XC2C32 - XC2C512) Coolrunner-ii CPLD Family
• Manufacturer: Xilinx

CoolRunner-II CPLD Family
Table 7: I/O Power-Up Characteristics
I/O Banking
CoolRunner-II CPLD 32 and 64 macrocell parts support a
single V
operation. Two V
256 macrocell parts where outputs on each rail can inde-
pendently range from 3.3V down to 1.5V operation. Four
V
parts with each rail independently supporting any voltage
between 3.3V and 1.5V. The V
for a CoolRunner-II CPLD must be maintained within 1.8V
±5% for correct speed operation and proper in system pro-
gramming.
Mixed Voltage, Power Sequencing, and
Hot Plugging
As mentioned in I/O Banking, CoolRunner-II CPLD parts
support mixed voltage I/O signals where signals within the
same bank can range from 3.3V down to 1.5V. The power
applied to the V
and the CoolRunner-II CPLD will not be damaged. For best
12
IOB Bus-Hold/Weak Pullup
Device Outputs
Device Inputs and Clocks
Function Block
JTAG Controller
CCIO
3.8 V
(Typ)
1.3V
(Typ)
0V
Figure 12: Device Behavior During Power Up
Power
Device Circuitry
V
rails are supported on the 384 and 512 macrocell
CCINT
No
CCIO
Quiescent
rail that can range from 3.3V down to 1.5V
State
CCIO
CCIO
and V
rails are supported on the 128 and
Initialization of User Registers
User Operation
CC
pins can occur in any order
CC
(internal supply voltage)
Quiescent State
Weak Pull-up
Disabled
Disabled
Disabled
Disabled
Quiescent
State
Power
x382_10
No
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Erased Device Operation
results, it is recommended that V
V
the board is inserted into a “live” connector (hot plugged)
and the parts will be well-behaved as if powering up in a
standard way.
Development System Support
Xilinx CoolRunner-II CPLDs are supported by all configura-
tions of Xilinx standard release development software as
well as the freely available WebFITTER and ISE WebPACK
software available from www.xilinx.com. Third party devel-
opment tools include synthesis tools from Cadence, Exem-
plar, Mentor Graphics, Synplicity, and Synopsys.
ATE Support
Third party ATE development support is available for both
programming and board/chip level testing. Vendors provid-
ing this support include Agilent, GenRad, and Teradyne.
Other third party providers are expected to deliver solutions
in the future.
CCIO
Weak Pull-up
Disabled
Disabled
Disabled
. CoolRunner-II CPLDs can reside on boards where
Enabled
Preliminary Product Specification
Bus-Hold/Weak Pullup
Valid User Operation
DS090 (v1.7) October 2, 2003
As Configured
As Configured
As Configured
CCINT
Enabled
be applied before
R