MT28F400B3 Micron Technology, MT28F400B3 Datasheet - Page 8

• Manufacturer Part Number: MT28F400B3
• Description: (MT28F004B3 / MT28F400B3) FLASH MEMORY
• Manufacturer: Micron Technology

what commands are allowed in this condition. See the
Command Execution section for more detail.
DEEP POWER-DOWN MODE
MT28F004B3 and MT28F400B3 feature a very low cur-
rent, deep power-down mode. To enter this mode, the
RP# pin is taken to V
draw is a maximum of 8µA at 3.3V V
power-down also clears the status register and sets the
ISM to the read array mode.
MEMORY ARCHITECTURE
architecture is designed to allow sections to be erased
without disturbing the rest of the array. The array is
divided into seven addressable blocks that vary in size
and are independently erasable. When blocks rather than
the entire array are erased, total device endurance is
enhanced, as is system flexibility. Only the ERASE func-
tion is block-oriented. All READ and WRITE operations
are done on a random-access basis.
or WRITE with a hardware protection circuit which re-
4Mb Smart 3 Boot Block Flash Memory
F45_3.p65 – Rev. 3, Pub. 12/01
To allow for maximum power conservation, the
The MT28F004B3 and MT28F400B3 memory array
The boot block is protected from unintentional ERASE
WORD ADDRESS
MT28F004B3/400B3xx-xxB
30000h
20000h
10000h
04000h
03000h
02000h
00000h
03FFFh
02FFFh
01FFFh
3FFFFh
2FFFFh
1FFFFh
0FFFFh
Bottom Boot
BYTE ADDRESS
SS
60000h
40000h
20000h
08000h
06000h
04000h
00000h
7FFFFh
5FFFFh
3FFFFh
1FFFFh
07FFFh
05FFFh
03FFFh
±0.2V. In this mode, the current
8KB Parameter Block
8KB Parameter Block
128KB Main Block
128KB Main Block
128KB Main Block
96KB Main Block
16KB Boot Block
CC
. Entering deep
Memory Address Maps
SMART 3 BOOT BLOCK FLASH MEMORY
Figure 1
8
quires that a super-voltage (V
the WP# pin be driven HIGH before erasure is com-
menced. The boot block is intended for the core firmware
required for basic system functionality. The remaining
six blocks do not require either of these two conditions be
met before WRITE or ERASE operations.
BOOT BLOCK
security for the most sensitive portions of the firmware.
This 16KB block may only be erased or written when the
RP# pin is at the specified boot block unlock voltage (V
of 12V or when the WP# pin is V
ERASE of the boot block, the RP# pin must be held at V
or the WP# pin held HIGH until the ERASE or WRITE is
completed. The V
the boot block is written to or erased.
two configurations and top or bottom boot block. The top
boot block version supports processors of the x86 variety.
The bottom boot block version is intended for 680X0 and
RISC applications. Figure 1 illustrates the memory ad-
dress maps associated with these two versions.
The hardware-protected boot block provides extra
The MT28F004B3 and MT28F400B3 are available in
WORD ADDRESS
MT28F004B3/400B3xx-xxT
Micron Technology, Inc., reserves the right to change products or specifications without notice.
3D000h
3C000h
3E000h
3DFFFh
30000h
20000h
10000h
00000h
3CFFFh
3BFFFh
3FFFFh
2FFFFh
1FFFFh
0FFFFh
PP
pin must be at V
BYTE ADDRESS
Top Boot
7A000h
7C000h
78000h
60000h
40000h
20000h
00000h
7BFFFh
7FFFFh
79FFFh
77FFFh
5FFFFh
3FFFFh
1FFFFh
HH
8KB Parameter Block
8KB Parameter Block
128KB Main Block
128KB Main Block
128KB Main Block
) be applied to RP# or that
96KB Main Block
16KB Boot Block
IH
. During a WRITE or
PPH
(3.3V or 5V) when
©2001, Micron Technology, Inc.
4Mb
HH
HH
)