MT28F800B3 Micron Technology, MT28F800B3 Datasheet - Page 16
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MT28F800B3
Manufacturer Part Number
MT28F800B3
Description
(MT28F008B3 / MT28F800B3) FLASH MEMORY
Manufacturer
Micron Technology
Datasheet
1.MT28F800B3.pdf
(30 pages)
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DataSheet4U.com
www.DataSheet4U.com
DataSheet
NOTE: 1. Sequence may be repeated to erase additional blocks.
8Mb Smart 3 Boot Block Flash Memory
Q10_3.p65 – Rev. 3, Pub. 10/01
4
SELF-TIMED BLOCK ERASE SEQUENCE
U
.com
STATUS REGISTER
ERASE Complete
Complete Status
Check (optional)
V
2. Complete status check is not required. However, if SR3 = 1, further ERASEs are inhibited until the status register is
3. To return to the array read mode, the FFh command must be issued.
4. Refer to the ERASE SUSPEND flowchart for more information.
5. If SR3 is set during a WRITE or BLOCK ERASE attempt, CLEAR STATUS REGISTER must be issued before further WRITE
6. Status register bits 3-5 must be cleared using CLEAR STATUS REGISTER.
Block Address
PP
WRITE D0h,
WRITE 20h
cleared.
or ERASE operations are allowed by the CEL.
= 3.3V or 5V
SR7 = 1?
READ
Start
YES
2
3
NO
Suspend ERASE?
YES
Sequence
Suspend
NO
ERASE Resumed
4
DataSheet4U.com
SMART 3 BOOT BLOCK FLASH MEMORY
1
16
Start (ERASE completed)
ERASE Successful
STATUS-CHECK SEQUENCE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
COMPLETE BLOCK ERASE
SR4, 5 = 1?
SR3 = 0?
SR5 = 0?
YES
YES
NO
YES
NO
NO
V
Command Sequence Error
BLOCK ERASE Error
PP
Error
5, 6
©2001, Micron Technology, Inc.
8Mb
6
6