MT28F008B5 Micron Technology, MT28F008B5 Datasheet - Page 10

• Manufacturer Part Number: MT28F008B5
• Description: (MT28F008B5 / MT28F800B5) FLASH MEMORY
• Manufacturer: Micron Technology

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DataSheet
INPUT OPERATIONS
array or to input a command to the CEL. A command
input issues an 8-bit command to the CEL to control
the mode of operation of the device. A WRITE is used
to input data to the memory array. The following sec-
tion describes both types of inputs. More information
describing how to use the two types of inputs to write
or erase the device is provided in the Command Execu-
tion section.
Commands
and CE# and WE# must be LOW. Addresses are “Don’t
Care” but must be held stable, except during an ERASE
CONFIRM (described in a later section). The 8-bit
command is input on DQ0–DQ7, while DQ8–DQ15 are
“Don’t Care” on the MT28F800B5. The command is
latched on the rising edge of CE# (CE#-controlled) or
WE# (WE#-controlled), whichever occurs first. The
condition of BYTE# has no effect on a command input.
Table 1:
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
COMMAND
RESERVED
READ ARRAY
IDENTIFY DEVICE
READ STATUS REGISTER
CLEAR STATUS REGISTER
ERASE SETUP
ERASE CONFIRM/RESUME
WRITE SETUP
ERASE SUSPEND
4
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The DQ pins are used either to input data to the
To perform a command input, OE# must be HIGH,
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Command Set
HEX CODE
40h or 10h
D0h
00h
90h
70h
50h
20h
B0h
FFh
DESCRIPTION
This command and all unlisted commands are invalid and should not be
called. These commands are reserved to allow for future feature
enhancements.
Must be issued after any other command cycle before the array can be read.
It is not necessary to issue this command after power-up or RESET.
Allows the device and manufacturer compatibility ID to be read. A0 is used
to decode between the manufacturer compatibility ID (A0 = LOW) and
device ID (A0 = HIGH).
Allows the status register to be read. Please refer to Table 2 for more
information on the status register bits.
Clears status register bits 3-5, which cannot be cleared by the ISM.
The first command given in the two-cycle ERASE sequence. The ERASE is not
completed unless followed by ERASE CONFIRM.
The second command given in the two-cycle ERASE sequence. Must follow
an ERASE SETUP command to be valid. Also used during an ERASE SUSPEND
to resume the ERASE.
The first command given in the two-cycle WRITE sequence. The write data
and address are given in the following cycle to complete the WRITE.
Requests a halt of the ERASE and puts the device into the erase suspend
mode. When the device is in this mode, only READ STATUS REGISTER, READ
ARRAY and ERASE RESUME commands may be executed.
DataSheet4U.com
SMART 5 BOOT BLOCK FLASH MEMORY
Memory Array
to logic 0s but cannot change a given bit to a logic 1
from a logic 0. Setting any bits to a logic 1 requires that
the entire block be erased. To perform a WRITE, OE#
must be HIGH, CE# and WE# must be LOW, and V
must be set to V
requires that the RP# pin be at V
A0–A18 (A19) provide the address to be written, while
the data to be written to the array is input on the DQ
pins. The data and addresses are latched on the rising
edge of CE# (CE#-controlled) or WE# (WE#-con-
trolled), whichever occurs first. A WRITE must be pre-
ceded by a WRITE SETUP command. Details on how to
input data to the array are described in the Write
Sequence section.
READs on the MT28F800B5. When BYTE# is LOW (byte
mode), data is input on DQ0–DQ7, DQ8–DQ14 are
High-Z, and DQ15 becomes the lowest order address
input. When BYTE# is HIGH (word mode), data is
input on DQ0–DQ15.
A WRITE to the memory array sets the desired bits
Selectable bus sizing applies to WRITEs as it does to
10
Micron Technology, Inc. Reserves the right to change products or specifications without notice.
PPH
. Writing to the boot block also
HH
or WP# be HIGH.
©2002, Micron Technology Inc.
8Mb
PP