MT28F200B5 Micron Technology, MT28F200B5 Datasheet - Page 4

• Manufacturer Part Number: MT28F200B5
• Description: (MT28F002B5 / MT28F200B5) FLASH MEMORY
• Manufacturer: Micron Technology

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DataSheet
PIN DESCRIPTIONS
NOTE: 1. For SmartVoltage-compatible production programming, 12V V
2Mb Smart 5 Boot Block Flash Memory
F50.p65 – Rev. 1/00
44-PIN SOP 40-PIN TSOP 48-PIN TSOP
4
11, 10, 9, 8,
NUMBERS
42, 41, 40,
39, 38, 37,
15, 17, 19,
21, 24, 26,
16, 18, 20,
22, 25, 27,
36, 35, 34
7, 6, 5, 4,
U
28, 30
13, 32
.com
43
12
44
14
33
31
23
29
2
1
3
be connected for up to 100 cumulative hours.
13, 29, 37, 38 9, 10, 15-17
36, 6, 5, 4, 3, 6, 5, 4, 3, 2,
25-28, 32-35
15, 14, 8, 7,
NUMBERS
21, 20, 19,
18, 17, 16,
2, 1, 40
30, 31
23, 39
12
22
10
24
11
9
–
–
–
19, 18, 8, 7,
NUMBERS
25, 24, 23,
22, 21, 20,
29, 31, 33,
35, 38, 40,
30, 32, 34,
36, 39, 41,
42, 44
27, 46
1, 48
11
14
26
12
28
47
45
43
13
37
DQ8-DQ14
SYMBOL
DQ0-DQ7
A0-A16/
BYTE#
(A - 1)
DQ15
(A17)
WE#
WP#
OE#
CE#
RP#
V
V
V
NC
CC
PP
SS
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SMART 5 BOOT BLOCK FLASH MEMORY
Output of address input when BYTE# = LOW during READ or WRITE
Output data input pins during a WRITE. These pins are used to input
Output data input pins during a WRITE when BYTE# = HIGH. These
Supply Write/Erase Supply Voltage: From a WRITE or ERASE CONFIRM
Supply Power Supply: +5V 10%.
Supply Ground.
Input/ Data I/O: MSB of data when BYTE# = HIGH. Address Input: LSB
Input/ Data I/Os: Data output pins during any READ operation or
Input/ Data I/Os: Data output pins during any READ operation or
TYPE
Input
Input
Input
Input
Input
Input
Input
–
4
Write Enable: Determines if a given cycle is a WRITE cycle. If
WE# is LOW, the cycle is either a WRITE to the command
execution logic (CEL) or to the memory array.
Write Protect: Unlocks the boot block when HIGH if V
V
ERASE. Does not affect WRITE or ERASE operation on other
blocks.
Chip Enable: Activates the device when LOW. When CE# is
HIGH, the device is disabled and goes into standby power
mode.
Reset/Power-Down: When LOW, RP# clears the status register,
sets the internal state machine (ISM) to the array read mode
and places the device in deep power-down mode. All inputs,
including CE#, are “Don’t Care,” and all outputs are High-Z.
RP# unlocks the boot block and overrides the condition of
WP# when at V
other modes of operation.
Output Enable: Enables data output buffers when LOW.
When OE# is HIGH, the output buffers are disabled.
Byte Enable: If BYTE# = HIGH, the upper byte is active through
DQ8-DQ15. If BYTE# = LOW, DQ8-DQ14 are High-Z, and all
data is accessed through DQ0-DQ7. DQ15/(A - 1) becomes the
least significant address input.
Address Inputs: Select a unique, 16-bit word or 8-bit byte. The
DQ15/(A - 1) input becomes the lowest order address when
BYTE# = LOW (MT28F200B5) to allow for a selection of an
8-bit byte from the 262,144 available.
operation.
commands to the CEL.
pins are High-Z when BYTE# is LOW.
until completion of the WRITE or ERASE, V
(5V) or V
operations.
No Connect: These pins may be driven or left unconnected.
PPH
1
(5V) or V
PP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
PPH
is supported for a maximum of 100 cycles and may
2
(12V)
PPH
HH
2
(12V), and must be held at V
1
(12V)
. V
PP
1
DESCRIPTION
= “Don’t Care” during all other
and RP# = V
IH
during a WRITE or
PP
must be at V
©2000, Micron Technology, Inc.
IH
during all
2Mb
PP
=
PPH
1
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