MT29F128G08WAAC6 Micron, MT29F128G08WAAC6 Datasheet - Page 60

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MT29F128G08WAAC6

Manufacturer Part Number
MT29F128G08WAAC6
Description
NAND Flash Memory
Manufacturer
Micron
Datasheet
Figure 36:
Figure 37:
TWO-PLANE PROGRAM PAGE CACHE MODE 80h-11h-80h-15h
PDF: 09005aef8278ee3f / Source: 09005aef81f17540
16gb_nand_mlc_l52a__2.fm -Rev. D 5/08 EN
R/B#
R/B#
I/Ox
I/Ox
R/B#
I/Ox
80h
1
80h
85h
Address (5 cycles)
1st-plane address
Repeat as many times as necessary
address than previous
TWO-PLANE PROGRAM PAGE
TWO-PLANE PROGRAM PAGE with RANDOM DATA INPUT
Address (5 cycles)
1st-plane address
5 address cycles, for
Different column
Address (2 cycles)
2nd plane only
Notes: 1. Command can be 70h or 78h.
Data
The TWO-PLANE PROGRAM PAGE CACHE MODE (80h-11h-80h-15h) operation is simi-
lar to the PROGRAM PAGE CACHE MODE (80h-15h) operation. It cache programs two
pages of data from the data registers to the NAND Flash arrays. The pages must be pro-
grammed to different planes on the same die. Within a block, the pages must be pro-
grammed consecutively from the least significant to the most significant page address.
Random page programming within a block is prohibited. The first-plane and second-
plane address must meet the two-plane addressing requirements (see “Two-Plane
Addressing” on page 55).
Data
Data
input
input
input
85h
11h
Micron Confidential and Proprietary
Repeat as many times as necessary
address than previous
5 address cycles, for
10h
Different column
Address (2 cycles)
t DBSY
1st plane only
t PROG
80h
2nd-plane address
60
Address (5 cycles)
Data
www.DataSheet.net/
input
16, 32, 64, 128Gb NAND Flash Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
11h
Data
t DBSY
input
80h
10h
Address (5 cycles)
2nd-plane address
Command Definitions
t PROG
©2005 Micron Technology, Inc. All rights reserved.
70h
1
Data
Status
input
1
Datasheet pdf - http://www.DataSheet4U.co.kr/

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