MT9046 Zarlink Semiconductor, MT9046 Datasheet - Page 7

• Manufacturer Part Number: MT9046
• Description: T1/E1 System Synchronizer with Holdover
• Manufacturer: Zarlink Semiconductor

Phase Detector - the Phase Detector compares the virtual reference signal from the TIE Corrector circuit with the
feedback signal from the Frequency Select MUX circuit, and provides an error signal corresponding to the phase
difference between the two. This error signal is passed to the Limiter circuit. The Frequency Select MUX allows the
proper feedback signal to be externally selected (e.g., 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz).
Limiter - the Limiter receives the error signal from the Phase Detector and ensures that the DPLL responds to all
input transient conditions with a maximum output phase slope of 5 ns per 125 us. This is well within the maximum
phase slope of 7.6 ns per 125 us or 81 ns per 1.326 ms specified by AT&T TR62411 and Bellcore GR-1244-CORE,
respectively.
Loop Filter - the Loop Filter is similar to a first order low pass filter with a 1.9 Hz cutoff frequency for all four
reference frequency selections (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz). This filter ensures that the jitter
transfer requirements in ETS 300 011 and AT&T TR62411 are met.
Control Circuit - the Control Circuit uses status and control information from the State Machine and the Input
Impairment Circuit to set the mode of the DPLL. The three possible modes are Normal, Holdover and Freerun.
Digitally Controlled Oscillator (DCO) - the DCO receives the limited and filtered signal from the Loop Filter, and
based on its value, generates a corresponding digital output signal. The synchronization method of the DCO is
dependent on the state of the MT9046.
In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the selected input
reference signal.
In Holdover Mode, the DCO is free running at a frequency equal to the last (less 30 ms to 60 ms) frequency the
DCO was generating while in Normal Mode.
In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the OSCi 20 MHz source.
Lock Indicator - If the PLL is in frequency lock (frequency lock means the center frequency of the PLL is identical to
the line frequency), and the input phase offset is small enough such that no phase slope limiting is exhibited, then
the lock signal will be set high. For specific Lock Indicator design recommendations see the Applications - Lock
Indicator section.
Output Interface Circuit
The output of the DCO (DPLL) is used by the Output Interface Circuit to provide the output signals shown in Figure
5. The Output Interface Circuit uses four Tapped Delay Lines followed by a T1 Divider Circuit, an E1 Divider Circuit,
and a DS2 Divider Circuit to generate the required output signals.
Four tapped delay lines are used to generate 16.384 MHz, 12.352 MHz, 12.624 MHz and 19.44 MHz signals.
Virtual Reference
TIE Corrector
from
Frequency Select MUX
Feedback Signal
Detector
Phase
from
Figure 4 - DPLL Block Diagram
Limiter
Zarlink Semiconductor Inc.
Input Impairment Monitor
MT9046
State Select
State Machine
from
State Select
7
Loop Filter
from
Controlled
Oscillator
Digitally
Control
Circuit
Output Interface Circuit
DPLL Reference
to
Data Sheet