MT9075A Mitel Networks Corporation, MT9075A Datasheet - Page 58

• Manufacturer Part Number: MT9075A
• Description: E1 Single Chip Transceiver
• Manufacturer: Mitel Networks Corporation

MT9075A
4-186
Bit
7
6
5
4
3
(Page 0BH &0CH, Address 13H) (continued)
Name
Adrec
RxEN
TxEN
EOP
FA
Table 83 - HDLC Control Register 1
Address Recognition. When one
this
recognition.
receiver to recognize only those
packets having the unique address
as programmed in the Receive
Address Recognition Registers or if
the address is an All call address.
Receive Enable. When one the
receiver will be immediately enabled
and will begin searching for flags,
Go-Aheads etc.
When zero this bit will disable the
HDLC receiver after the rest of the
packet presently being received is
finished. The receiver internal clock
is disabled.
Transmit Enable. When one the
transmitter
enabled and will begin transmitting
data, if any, or go to a mark idle or
interframe time fill state.
When zero this bit will disable the
HDLC
completion of the packet presently
being transmitted. The transmitter
internal clock is disabled.
End Of Packet. Forms a tag on the
next byte written the TX FIFO, and
when set will indicate an end of
packet byte to the transmitter, which
will transmit an FCS following this
byte. This facilitates loading of
multiple packets into TX FIFO.
Reset automatically after a write to
the TX FIFO occurs.
Frame Abort. Forms a tag on the
next byte written to the TX FIFO,
and when set to one FA will indicate
to the transmitter that it should abort
the packet in which that byte is
being
automatically after a write to the TX
FIFO.
Functional Description
bit
transmitter
transmitted.
will
will
This
enable
be
forces
immediately
after
address
Reset
the
the
(Pages 0BH & 0CH, Address 14H) (Continued)
5, 4 RQ9, RQ8 Byte Status bits from RX FIFO.
1-0
Bit
Bit
7
6
2
Mark-Idle When zero, the transmitter will be in
Table 84 - HDLC Status Register
Idle Chan Idle Channel. This bit is set to a 1
Name
Table 83 - HDLC Control Register 1
Name
Intgen
RSV
(Page 0BH &0CH, Address 13H)
an idle state. When one it is in an
interframe time fill state. These two
states will only occur when the TX
FIFO is empty.
Reserved: Must be set to 0 for
normal operation.
Interrupt Generation. Intgen is set
to
conjunction with the Interrupt Mask
Register) has been generated by
the HDLC. This is an asynchronous
event. It is reset when the Interrupt
Register is read.
when an idle Channel state (15 or
more ones) has been detected at
the
asynchronous
becomes valid after the first 15 bits
or the first zero is received.
These bits determine the status of
the byte to be read from RX FIFO
as follows:
RQ9
0
0
1
1
Preliminary Information
1
Functional Description
Functional Description
receiver.
RQ8
when
0
1
0
1
Packet byte.
First byte.
Last byte of a good
packet.
Last byte of a bad
packet.
an
event.
Byte Status
This
interrupt
is
Status
(in
an