MT90871 Zarlink Semiconductor, MT90871 Datasheet - Page 41

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MT90871

Manufacturer Part Number
MT90871
Description
Flexible 8K Digital Switch (F8KDX)
Manufacturer
Zarlink Semiconductor
Datasheet

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Data Sheet
13.6
Address 0043h to 0052h
Sixteen Backplane input channel delay registers (BCDR0 to BCDR15) allow users to program the input channel
delay for the Backplane input data streams BSTi0-15. The possible adjustment is 255 channels and the BCDR0 to
BCDR15 registers are configured as follows:
13.6.1
These eight bits define the delay, in channel numbers, the serial interface receiver takes to store the channel data
from the Backplane stream input pins. The input channel delay can be set to 255 (16Mb/s streams), 127 (8Mb/s
streams), 63 (4Mb/s streams) or 31 (2Mb/s streams) from the frame boundary.
(where n = 0 to 15 )
BCDRn Bit
15-8
7-0
Backplane Input Channel Delay Registers (BCDR0 to BCDR15)
Backplane Channel Delay Bits 8-0 (BCDn8 - BCDn0)
Data Rate
4 1/2
4 3/4
5 1/4
5 1/2
5 3/4
6 1/4
6 1/2
6 3/4
7 1/4
7 1/2
7 3/4
Table 19- Local Input Bit Delay Programming Table (continued)
5
6
7
Table 20- Backplane Channel Delay Register (BCDRn) Bits
Reserved
BCD(7:0)
Name
LID4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Zarlink Semiconductor Inc.
Reset
LID3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Corresponding Delay Bits
Reserved
Backplane Channel Delay Register
The binary value of these bits refers to the channel
delay value for the Backplane input stream
LID2
0
0
1
1
1
1
0
0
0
0
1
1
1
1
LID1
Description
1
1
0
0
1
1
0
0
1
1
0
0
1
1
LID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
41

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